Rose Thompson 2241976d29 Updated mmu to not generate trap on cacheable misaligned access when supported. ... Updated tests with David's help.		2023-10-30 18:26:11 -05:00
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coverage	tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker	2023-09-02 12:56:36 -07:00
custom	Fixed issue when with flush miss.	2023-08-18 16:36:13 -05:00
fp	fixed bug in testvector extract script	2023-06-22 09:13:22 -07:00
riscof	minfo test working again with mconfigptr for RV64	2023-10-15 06:41:52 -07:00
testgen	Added RVTEST_CASE to testgen header	2023-02-09 18:25:24 -08:00
wally-riscv-arch-test	Updated mmu to not generate trap on cacheable misaligned access when supported.	2023-10-30 18:26:11 -05:00