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Fixed timer interrupt testing

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This commit is contained in:
David Harris 2023-06-09 17:20:41 -07:00
parent f68b9c224a
commit c137a1c8cf
6 changed files with 13 additions and 10 deletions
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3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1,5 +1,6 @@
FFFFFFFF # stimecmp readback
80000000 # menvcfg readback
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
80000000 # readback value from writing menvcfgh
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0

3
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -280,8 +280,7 @@ end_trap_triggers:
la t4, 0x02004000 // MTIMECMP register in CLINT
li t5, 0xFFFFFFFF
sw t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
csrw stimecmp, t5 // also set stimecmp to avoid an immediate supervisor timer interrupt
j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
// ---------------------------------------------------------------------------------------------

5
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
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@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Sstc_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
INIT_TESTS
@ -34,8 +34,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
WRITE_READ_CSR menvcfgh, 0x80000000 // Enable menvcfg.STCE
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1,7 +1,9 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
FFFFFFFF # stimecmp low bits
00000000 # stimecmp high bits
00000000 # menvcfg low bits
80000000 # menvcfg high bits
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000
00000000 # mtval of faulting instruction address (0x0)

1
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
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@ -274,7 +274,6 @@ end_trap_triggers:
la t4, 0x02004000 // MTIMECMP register in CLINT
li t5, 0xFFFFFFFF
sd t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
csrw stimecmp, t5 // also set stimecmp to avoid an immediate supervisor timer interrupt
j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.

5
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
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@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Sstc_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
INIT_TESTS
@ -33,8 +33,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
WRITE_READ_CSR menvcfg, 0x8000000000000000 // Enable menvcfg.STCE
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests