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458 Commits

Author SHA1 Message Date
Katherine Parry
4db7f3065c FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
06af239e6c FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
1d3db5ead5 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
bbracker
979a9bf037 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
44dc665fc5 Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
David Harris
26531f2634 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
Katherine Parry
9464c9022d floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
bbracker
f00eb22700 fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
e4c90f503a regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
James E. Stine
daf780b9c2 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
Domenico Ottolia
88ab07d456 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
ushakya22
682bc7b58e Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Domenico Ottolia
8398e653dd Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
ushakya22
46f20745d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
b805b98a8c Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Domenico Ottolia
1673ad6e27 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
45b0af497c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
d68fe44446 Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
41a19153cc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
67c7bfe34d Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
Domenico Ottolia
973f32da47 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
a3b5ae9742 Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
ad40464557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
803a69efe6 Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
2669a6a0db Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
4d70e22a6a Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
997c9ad5c0 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
780ad3eaf4 working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
c5a306426a finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
b7159652f6 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
968994c04a updated pipeline tests 2021-05-03 22:07:36 -04:00
Elizabeth Hedenberg
2d1d929485 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
2a33673e3c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
463ba1a2be coremark directory changes 2021-05-03 19:35:06 -04:00
David Harris
d7438929d4 Extended maximum signature length to 1M 2021-05-03 15:29:20 -04:00
bbracker
2368b58cc9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 09:23:52 -04:00
Noah Boorstin
b32128465c busybear: remove now unneeded hack for fixed CSR issue 2021-05-01 15:17:04 -04:00
Katherine Parry
db95151d8d fpu imperas tests run 2021-05-01 02:18:01 +00:00
bbracker
1fcd43e844 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Domenico Ottolia
d03ca20dc9 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Ross Thompson
818c0abc89 Fixed memory size in configs for rv32ic and rv64ic. 
Removed warning on call to $fscanf.
 2021-04-29 17:36:46 -05:00
Domenico Ottolia
c60c4f4adc Minor improvements to scause test 2021-04-29 16:48:07 -04:00
Domenico Ottolia
c8a81779ca Add machine-mode timer interrupts to mcause tests 2021-04-29 16:39:18 -04:00
Domenico Ottolia
6fc04768f5 Same but don't break sim-wally this time 2021-04-29 15:33:27 -04:00
Domenico Ottolia
7ae5d4d11e Add more exceptions to medeleg tests 2021-04-29 15:32:13 -04:00
ushakya22
77210527c1 Working MIE timer tests 2021-04-29 15:19:43 -04:00
Domenico Ottolia
4fae8088e3 Add medeleg tests 2021-04-29 15:02:36 -04:00
Noah Boorstin
a4dad3403e same but do that right this time 2021-04-28 14:27:28 -04:00
Noah Boorstin
44606b6c19 busybear: respect branch predictor disable config 2021-04-27 15:52:18 -04:00
Ross Thompson
8ae28e7887 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
ff1a6b63ed ok but do that better 2021-04-26 14:38:05 -04:00
Noah Boorstin
0324329ed9 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Noah Boorstin
ee628e388a minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
8e5409af66 Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
31a0387136 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
ba94fa3436 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
86946266cf thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
e3672ca23f Add address translation to busybear testbench 2021-04-23 20:12:20 -04:00
Noah Boorstin
09755251bc busybear 2021-04-23 17:32:37 -04:00
Shriya Nadgauda
c66e63ff70 adding pipeline testing 2021-04-23 14:19:17 -04:00
Ross Thompson
020fb65adf Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Thomas Fleming
6acaa313b5 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
Noah Boorstin
cd7ea29ce6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Domenico Ottolia
44da1488ff Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
f63f16f486 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
bf86a809eb Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
251ece20fe Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Noah Boorstin
3f0ead9d4e yay buildroot passes a decent amount of tests now 
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
 2021-04-19 03:26:08 -04:00
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Noah Boorstin
2af4e2f4ac slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
9bb1233433 neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
bbracker
290b3424e5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
531423d7e1 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Jarred Allen
81c02bda55 Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Thomas Fleming
3c49fd08f6 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
c1e2e58ebe Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
d66fcbc4ab busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41 busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
bbracker
1ee8feffe5 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
755e2e5771 merge testbench 2021-04-08 14:28:01 -04:00
Noah Boorstin
14d2ad1e2d try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
4322694f7a Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Domenico Ottolia
60cf38192b Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
465d3986b0 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
c91436d3b7 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
bff2d61a1f Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Noah Boorstin
284d583877 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
dbd5a4320e Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
f4e5642c62 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Katherine Parry
d7b1379ab8 Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
0595ae983f Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
38a0199260 Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Noah Boorstin
75f58c4df5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
6e83ccc3c4 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
637bba6509 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
e43849b82c Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Ross Thompson
11109e5a88 Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Ross Thompson
5edc90b1c2 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
9e61481414 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
e1842c8da6 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
69e5319675 busybear: more progress 2021-03-23 14:49:30 -04:00
Noah Boorstin
24e403bc35 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
f3194c6388 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Noah Boorstin
d5bd5fa9d7 start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
15474f678d Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
849641f31e busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
2aa76b27e1 busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
3f897bbf53 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
74bcd9b994 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
5b1db9b6a2 Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
097e8edb3d Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
09faa40eb6 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Teo Ene
57f1ca5259 Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0 adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e69376c823 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
3e849f99a6 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
dfe6df2e00 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
da758e9e14 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
3618a39087 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Noah Boorstin
bfa7aedd35 busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Domenico Ottolia
d354cbd37d Add privileged testbench 2021-03-16 20:28:38 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
36452749d7 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
400791163e copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
7ceef2b0c6 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
David Harris
56b690ccb9 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359 Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
a8b242a6ef busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Jarred Allen
4757794887 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
845115302e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Ross Thompson
50a92247b3 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
3172be3039 More progress 2021-03-09 21:16:07 -05:00
David Harris
c2f340681d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
4a8b689f62 busybear: better NOPing out of float instructions 2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
93c9c57426 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00