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571 Commits

Author SHA1 Message Date
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
David Harris
2819a1c305 Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
812b56acc6 Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
de5b61291f Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Ross Thompson
059c04e2a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
2436534687 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
83d283354c Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
16b3c64234 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
855d68afde WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
2294cbc1c6 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Katherine Parry
c307cff503 fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Ross Thompson
9517fe9faf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
20885f4dea generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
0ed34b8e63 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
0806d1a134 Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
d83db2cde5 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
fd9a33e453 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
David Harris
6966554ee8 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
d135866098 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
5ef6cde52e Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
f58a1eff9e Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
178ecaa451 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
0340c0fd44 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
36c30b14c1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
e60139d3ee fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
cb945a6a6a Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
1586f893b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
7e05935348 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
e81f317764 Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
d32e1147bf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
34c94f150e simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
2ed1c9f14f Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
fb0eec0f76 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
0942429b7f Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
a6d090a7c0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
dc48d84dd6 Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
93d6b2fb62 Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
f917ed7ed0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
54b9745a75 big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
b2a77da96b Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
44f94173bf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
Ross Thompson
3ac736e2d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
370a075fa1 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
1993069986 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
fc2b4453ec rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
de2672231d Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
David Harris
057ee56d7e Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
049c55769a fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
ad106e7130 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
bbracker
46ffa4b079 fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
dc9635b757 fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Ross Thompson
7099259ff7 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
7a824eaae1 Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
150a7b234b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
9f60256f22 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
58668812c1 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
abdbc31d14 fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Katherine Parry
ead88fba55 fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
6ab14d7302 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
c5be2cb1d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Katherine Parry
c3c764a171 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
cec7625d91 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
d347de8c49 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
81a2fbb6d2 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445 Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
5c16b65a16 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
543e10ab32 Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
54abd944e2 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
b1340653cf bit write update 2022-03-09 19:09:20 +00:00
David Harris
004853c312 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
ba9320d822 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
2a8a1cd191 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
ac9528b450 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
ed32801cc1 Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
534fd70f76 Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
5d0b9bab6e Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
cfa82efccc fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
acd60218b8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7 Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
David Harris
d2282d5e87 Checked in fma16_template.v 2022-03-06 13:29:35 +00:00
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
David Harris
545f569f78 Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
8fbdbba81a fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
be2f668867 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
01e0f2f0d2 update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
David Harris
3bea7bb431 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
David Harris
1661983345 FMA project ready to start 2022-03-01 20:58:08 +00:00
David Harris
f314e60dc8 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
f0a7ae2bba adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
e108eb5195 Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
bb14dba9be Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
c7b5d32a72 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
c6561d1e8b Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
274ecf13ad Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
5a5142c14f fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
d917cc1379 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
8a55935456 simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
1852eccaab Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac Added start of fma 2022-02-26 19:51:19 +00:00
Ross Thompson
97d64201f7 Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287 Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
6a52f95cc8 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
a6047697c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
e7934c585a change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279 Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
56fc6d0d7c Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
Ross Thompson
f48b12b089 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
cbf4395457 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 09:06:09 -06:00
Ross Thompson
ae06785b9f Minor changes to LSU. 2022-02-19 14:38:17 -06:00
David Harris
20a5798f43 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-18 23:08:47 +00:00
David Harris
6a0ffff05d Removed problematic warning about reaching default state in HPTW 2022-02-18 23:08:40 +00:00
Ross Thompson
6cd9d84e7f New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
ad237b3ce5 Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
Ross Thompson
cbac34943c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-17 14:49:37 -06:00
Ross Thompson
0eec096474 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00
David Harris
f3c7025ade Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
c9e33208e3 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e Cleaned warning on HPTW default state 2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd Register file comments about reset 2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 09:48:16 -06:00
David Harris
aa990be959 removed csrn and all of its outputs because depricated 2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3 Mostly removed N_SUPPORTED 2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
Ross Thompson
fcbb577f31 Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
David Harris
caa4d83e57 t push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5 More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63 More cache cleanup. 2022-02-13 12:38:39 -06:00
David Harris
f5678e25db Synthesis cleanup 2022-02-12 06:25:12 +00:00
David Harris
b537df2651 Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07 Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
20456097cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60 Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618 Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
Ross Thompson
f23817bf69 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9 Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05 More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7 Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22 Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
01126535db Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
d1d014bf1d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
13561c67bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
cecbb3362d rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
3e16730226 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
d5d9bb9d4d Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
Ross Thompson
3cd067ac6a Finished merge. 2022-02-08 11:36:24 -06:00
Ross Thompson
492c1473f3 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
096242a6d8 Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
Ross Thompson
190d619940 cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1 more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875 Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
fcd43ea004 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
e72d54ea98 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571 More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473 Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
c21eb67a07 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
Ross Thompson
1766c0f5ba Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
23868a33bc Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6 Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
c3122ce214 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
0e1d784b60 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
eb8dd5e7d7 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
5f7326368e cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
9b6a4d1d52 cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
0fbc32204c cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
c22f7eb11c cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
e92461159d cache cleanup 2022-02-03 15:36:11 +00:00
David Harris
9e0055cbb9 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73 changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
c12407ba6a Removed Busybear dependencies 2022-02-02 20:28:21 +00:00