Ross Thompson 1993069986 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.		2022-03-30 11:04:15 -05:00
..
cache	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
ebu	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
fma	Refactored SRAM bit write enable	2022-03-09 17:49:28 +00:00
fpu	fixed typo in unpack.sv	2022-03-23 18:26:59 +00:00
generic	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
ifu	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
lsu	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
mmu	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.	2022-03-22 22:04:06 -05:00
uncore	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
wally	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00