bbracker e7934c585a change RX side of UART to aslo be LSB-first		2022-02-22 03:34:08 +00:00
..
cache	Cache mods to be consistant with diagrams.	2022-02-14 12:40:51 -06:00
ebu	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
fpu	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
generic	RAM simplification	2022-02-08 20:15:23 +00:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Register file comments about reset	2022-02-16 17:21:05 +00:00
ifu	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
lsu	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
mmu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-18 23:08:47 +00:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Cleaned warning on HPTW default state	2022-02-16 17:40:13 +00:00
uncore	change RX side of UART to aslo be LSB-first	2022-02-22 03:34:08 +00:00
wally	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00