David Harris 096242a6d8 Merged TIM and regular testbenches. RV32e now working and back in regression.		2022-02-08 12:18:13 +00:00
..
cache	Reverted cache change	2022-02-07 14:47:20 +00:00
ebu	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
fpu	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
generic	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.	2022-01-26 18:23:39 -06:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
ifu	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
lsu	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
mmu	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
uncore	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
wally	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00