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960 Commits

Author SHA1 Message Date
Rose Thompson
84d86b1994 Fixed spill bugs in the aligner. 2023-11-10 17:18:45 -06:00
David Harris
3108b58290 Simplified integer postnormalization shift 2023-11-10 14:55:36 -08:00
David Harris
b315ead575 Simplified IntDivNormShift 2023-11-10 14:28:57 -08:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
Rose Thompson
9abd26aad9 Fixed bug which broke the non Zicclsm configs. 2023-11-10 16:08:04 -06:00
David Harris
2903791820 Simplified cycle count logic 2023-11-10 14:00:27 -08:00
David Harris
8f87860146 Reduced duplicated logic in fdivsqrtcycles 2023-11-10 11:25:54 -08:00
David Harris
255873a50c Divsqrt cleanup: change Q to U, commenting code 2023-11-10 11:21:02 -08:00
David Harris
953c53d065 fdivsqrt parameter cleanup 2023-11-10 09:11:15 -08:00
David Harris
4c106215f4 Started cleaning up shifting leading 1 in fdivsqrt 2023-11-10 08:46:55 -08:00
naichewa
5ce16dcb63 Cleanup 2023-11-09 16:52:55 -08:00
naichewa
3052a68d84 Remove old 2/4 bit logic, add comments, 
clean up unused signals
 2023-11-09 16:48:11 -08:00
naichewa
b13b8feee4 updated to-do comments 2023-11-08 15:28:51 -08:00
naichewa
d67badfc60 fix hardware interlock, hold mode deassert 2023-11-08 15:20:51 -08:00
Rose Thompson
44c60a3e76 Merge pull request #455 from davidharrishmc/dev 
Bit manipulation imperas config, fsqrt code changes to match chapter
 2023-11-08 08:27:15 -08:00
naichewa
a5837eb62c fifo fixes and edge case testing 2023-11-07 17:59:46 -08:00
David Harris
637cc3b78a Reparitioned sign logic in fdivsqrt to match paper 2023-11-06 14:11:42 -08:00
David Harris
4de21c206f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-03 16:04:10 -07:00
naichewa
6cdeb671bb Merge branch 'main' into spi 2023-11-03 13:15:15 -07:00
David Harris
7a56a66927 set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t 2023-11-03 06:37:05 -07:00
David Harris
1f2899de14 Modified rams to take USE_SRAM rather than P to facilitate synthesis 2023-11-03 05:44:13 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
David Harris
402538e13c Temporary fix of InstrM to prevent testbench hanging 2023-11-03 04:59:44 -07:00
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
naichewa
29e42b21df added test cases 2023-11-02 15:42:28 -07:00
Rose Thompson
0a4ed5515b Merge branch 'main' into Zicclsm 2023-11-02 12:55:51 -05:00
Rose Thompson
13333d3e82 Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup. 2023-11-01 14:25:18 -05:00
naichewa
a08356fdaa correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
David Harris
31d9ec08cb Improved comments about memory read paths 2023-11-01 07:00:17 -07:00
naichewa
9aa8a7af3e comments, more test cases 2023-11-01 01:26:34 -07:00
Rose Thompson
5660eff57d Working through issues with the psill logic. 2023-10-31 18:50:13 -05:00
naichewa
fefb5adb8f code review harris 2023-10-31 12:27:41 -07:00
David Harris
680fb3f30b Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
afabc52b61 Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
2d17a991d8 rom1p1r code cleanup 2023-10-30 19:47:49 -07:00
David Harris
3f7c67882f rom1p1r code cleanup 2023-10-30 19:46:38 -07:00
David Harris
90a178e31e Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
naichewa
7dd3f24d6c Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Rose Thompson
2241976d29 Updated mmu to not generate trap on cacheable misaligned access when supported. 
Updated tests with David's help.
 2023-10-30 18:26:11 -05:00
Rose Thompson
f13b67b869 Preemptively fixed the bytemask bug before testing. 2023-10-30 15:47:46 -05:00
Rose Thompson
b5763e11e8 rv32gc now also works with the alignment module. Still not tested with misligned access. 2023-10-30 15:30:09 -05:00
Rose Thompson
9cd2e47783 Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests. 2023-10-30 14:54:58 -05:00
Rose Thompson
569e3dc906 Finally lints cleanly. 2023-10-30 14:00:49 -05:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
27b8ebb9bd Fix issue 444 by preventing delegation of misaligned instructions when compressed instructions are supported. 2023-10-30 07:06:34 -07:00
Rose Thompson
dce3c85105 Progress. 2023-10-27 16:31:22 -05:00
Rose Thompson
747f453bb5 Passes lint with some exceptions. Still need to add misaligned store support. 2023-10-27 14:41:42 -05:00
Rose Thompson
36ca64c567 At least have the aligner integrated, but not tested. 2023-10-27 13:55:16 -05:00
Rose Thompson
657409aec5 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
Rose Thompson
6041bf20b3 The misaligned load alignment lints. 2023-10-27 11:41:49 -05:00
Rose Thompson
834c0df697 Added file. 2023-10-27 09:49:44 -05:00
Rose Thompson
449abef823 Progress on misaligned load/stores. 2023-10-27 09:35:44 -05:00
David Harris
734bf021d7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
Rose Thompson
06b5a92eff Updated comments about Interrupt and wfi. 2023-10-26 12:24:36 -05:00
Rose Thompson
4cd0584a11 Forgot to include this file in the last commit. 2023-10-26 12:20:42 -05:00
Rose Thompson
12763b7297 begin implemenation of Zicclsm. 2023-10-26 11:51:20 -05:00
Rose Thompson
3322ff915e Cleaned up the implementation changes for wfi. 2023-10-24 23:11:48 -05:00
Rose Thompson
c58f04c901 This version passes the regression test and solves issue #200. wfi's implemenation is changed so that wfi does not take an interrupt in the Memory stage. Instead it advances to the Writeback stage then traps. 2023-10-24 22:58:26 -05:00
Rose Thompson
c61526d034 Possible fix for wfi. 2023-10-24 18:08:33 -05:00
David Harris
3bb7539429 Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
Rose Thompson
694ec18934 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
1611d5ec3c Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
David Harris
6e7c0547a1 Modified log2 coding to avoid synthesis warning 2023-10-19 11:16:02 -07:00
David Harris
48d42c1e7c Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates 2023-10-18 05:50:41 -07:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
naichewa
aa5abfc8e8 always working after reg bit swizzle changes 2023-10-13 14:22:32 -07:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Ross Thompson
e02d3577ec Fixed issue #412 
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss.  The HPTW hits all entries in the D$ and quickly faults.  However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.

The simplest solution is to use CommittedF to delay Exceptions like with Interrupts.  Note this cannot happen with CommittedM.  If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
 2023-10-09 16:03:37 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
19a6bbb01b UpdateDA cleanup: don't assert UpdateDA when there is no SVADU 2023-10-04 09:57:13 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
Ross Thompson
f863cbf366 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
Ross Thompson
aeacb481aa Fixed sutble RAS bug when the stack size was not a power of 2. 2023-09-27 12:00:47 -05:00
Ross Thompson
26e4f6c6ba Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-09-14 10:16:54 -05:00
Ross Thompson
11a3fd9314 Slight modification to cachefsm. 2023-09-05 14:07:58 -05:00
Ross Thompson
22c519f2df Merge pull request #407 from davidharrishmc/dev 
initial spill logic improvement
 2023-09-05 13:29:37 -05:00
Ross Thompson
85ba53eeaf Merge pull request #406 from magpyed/cachesim_fix 
Properly gate LRUWriteEn with ~FlushStage
 2023-09-05 11:10:58 -05:00
David Harris
8f12c6f9a1 initial spill logic improvement 2023-09-03 04:21:13 -07:00
David Harris
9747d122d2 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
Limnanthes Serafini
6c78942685 Properly gate LRUWriteEn with ~FlushStage 2023-09-01 23:31:02 -07:00
David Harris
e75ceb044f Improved tlb and controller coverage; fixed exclusions on broken lines 2023-08-31 00:27:47 -07:00
Kevin Kim
e4b0ab1472 Merge branch 'openhwgroup:main' into synth_wrapper_gen 2023-08-28 09:03:10 -07:00
Kevin Kim
ea46280146 make synth integerates wrapper generation and runs synth on wrapper 2023-08-28 09:02:56 -07:00
Ross Thompson
d892afc574 Merge pull request #398 from davidharrishmc/dev 
Completed basic tests of svnapot and svpbmt
 2023-08-28 09:10:20 -05:00
David Harris
8d3ff59673 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
Kevin Kim
dabd15e029 synth works 2023-08-26 21:11:21 -07:00
David Harris
7a092a2275 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
f7b50f4721 Preparing to merge with CBO* changes 2023-08-25 18:41:03 -07:00
David Harris
bd6eef2a51 Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
David Harris
0e16203cd8 Merge pull request #393 from ross144/main 
Implemented and tested CBOZ instruction
 2023-08-24 19:17:38 -07:00
David Harris
c45fbe1ffe Merge pull request #394 from harshinisrinath1001/main 
Improved testing of csri with priv.S!
 2023-08-24 19:16:50 -07:00
harshinisrinath
c9112ff18d Improved testing of csri with priv.S 2023-08-24 18:39:15 -07:00
Ross Thompson
99455ad851 Fixed minor performance bug with CBOZ. 2023-08-24 17:08:20 -05:00
Ross Thompson
914b6f9734 Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00