David Harris
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9f40da54d4
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-21 16:43:07 -08:00 |
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David Harris
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d8186b9f58
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Swap in branch predictor simulator handling compressed instruction offsets
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2023-11-21 16:42:41 -08:00 |
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David Harris
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ed23ecc839
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Merge pull request #496 from ross144/main
Updated Linux Makefile to support generating vmlinux and disassembly required for questa
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2023-11-21 16:25:16 -08:00 |
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Rose Thompson
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a7f3517981
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Removed testing hack.
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2023-11-21 18:24:45 -06:00 |
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Rose Thompson
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29db402562
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-21 18:20:47 -06:00 |
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Rose Thompson
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6461f0fa63
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Fix to linux makefile to support disassembly and creating vmlinux automatically.
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2023-11-21 18:20:37 -06:00 |
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David Harris
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93a0db1fca
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swapped branch predictor simulator
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2023-11-21 15:02:09 -08:00 |
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David Harris
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3f3c20a38f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-21 14:04:02 -08:00 |
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David Harris
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2a3d87ca0f
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Merge pull request #495 from ross144/main
updates to imperas.ic for updated venture id and arch id.
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2023-11-21 14:03:51 -08:00 |
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Rose Thompson
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c08d5485ce
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Updates to buildroot config.
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2023-11-21 16:01:42 -06:00 |
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Rose Thompson
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4aa254fd3e
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-21 15:56:47 -06:00 |
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David Harris
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b5f79c44f9
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Reset STIMECMP to 0 to agree with ImperasDV
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2023-11-21 13:43:51 -08:00 |
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Rose Thompson
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e5b7301ffe
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Updated imperad dv vendor id and architecture id config.
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2023-11-21 15:14:17 -06:00 |
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Rose Thompson
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1dac4d221e
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Disable the trace for normal operation.
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2023-11-21 13:49:07 -06:00 |
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Rose Thompson
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c77a47b403
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Output the instruction trace to the logs directory.
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2023-11-21 13:47:58 -06:00 |
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Rose Thompson
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d57ec045de
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-21 13:46:45 -06:00 |
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Rose Thompson
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f82f7d9323
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Updated qemu scripts for updated linux build.
expanded memory from 128MB to 256MB.
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2023-11-21 13:46:37 -06:00 |
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Rose Thompson
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b02bd6c835
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Finally we got the wally tracer working with linux.
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2023-11-21 13:45:55 -06:00 |
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Rose Thompson
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3fd6d3464c
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We are logging now.
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2023-11-21 13:02:34 -06:00 |
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Rose Thompson
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6ff8d19157
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Added code to the wallyTracer to support outputing an instruction trace.
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2023-11-21 12:28:19 -06:00 |
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David Harris
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7f62905a71
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Merge pull request #494 from ross144/main
CBO simplifications
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2023-11-21 10:00:34 -08:00 |
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Rose Thompson
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58d89cc347
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-21 10:48:05 -06:00 |
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Rose Thompson
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add7fecb72
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-21 10:40:01 -06:00 |
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Rose Thompson
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386cf3eb56
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Merge pull request #493 from stineje/main
marchid approved by RISC-V
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2023-11-21 08:33:07 -08:00 |
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Rose Thompson
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24536fb1c6
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Merge pull request #492 from davidharrishmc/dev
Clean up unused signals, other cleanup
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2023-11-21 08:32:19 -08:00 |
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James E. Stine
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776eec16ae
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Update ppaAnalyze for recent update to put back parsing name
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2023-11-21 09:24:07 -06:00 |
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James E. Stine
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141cbd3f9f
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Update marchid/mvendorid for CV-Wally
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2023-11-21 09:23:02 -06:00 |
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David Harris
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2b2016271a
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repo cleanup and start to add CMO tests
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2023-11-20 23:41:36 -08:00 |
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David Harris
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d3ce683e06
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Removed other unused signals from Verilog
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2023-11-20 23:37:56 -08:00 |
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David Harris
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f89fd8a7fe
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removed unused cache signals
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2023-11-20 23:16:35 -08:00 |
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Rose Thompson
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1acc3951c8
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More simplifications.
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2023-11-21 00:19:24 -06:00 |
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Rose Thompson
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1d811b085c
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More cleanup.
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2023-11-21 00:14:59 -06:00 |
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Rose Thompson
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d2a747bf3d
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cleanup.
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2023-11-20 23:59:40 -06:00 |
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Rose Thompson
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70eb110a9c
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More optimizations to simplify cmo logic.
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2023-11-20 22:13:31 -06:00 |
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Rose Thompson
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52ac07ce8d
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Removed the CMO_WRITEBACK state from the cache and unused signals.
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2023-11-20 20:56:30 -06:00 |
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Rose Thompson
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5fb3c83efc
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Removed the CMO_WRITEBACK state from the cache.
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2023-11-20 20:52:11 -06:00 |
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Rose Thompson
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667fe035c0
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Simplified CMO.Zero fsm implementation slightly.
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2023-11-20 17:01:43 -06:00 |
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David Harris
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739c7f3f1c
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Merge pull request #491 from ross144/main
Running ImperasDV Linux is upto date
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2023-11-20 10:28:05 -08:00 |
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Rose Thompson
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eed6f11df6
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-20 11:29:45 -06:00 |
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Rose Thompson
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23e05cb8b2
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Finally have the cbo way muxing controls reduced to something sane.
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2023-11-20 11:28:03 -06:00 |
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Rose Thompson
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b137759b45
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-11-20 10:34:36 -06:00 |
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Rose Thompson
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64e627841a
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-20 10:30:42 -06:00 |
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Rose Thompson
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3594c08d4b
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Modified linux imperas tests to
1. enable zicclsm
2. enable logging at 7000 ms
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2023-11-20 10:30:35 -06:00 |
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Rose Thompson
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17e91f31f6
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Merge pull request #490 from davidharrishmc/dev
Synthesis running for textbook, preload IROM to avoid it being optimized out, updated M tests in risk-arch-test
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2023-11-19 20:42:29 -08:00 |
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David Harris
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8cb433cb66
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Commented IROM preloading
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2023-11-19 19:33:57 -08:00 |
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Rose Thompson
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cdd21d6635
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Added menvcfg to debugger for checking what linux has configured.
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2023-11-19 13:44:22 -06:00 |
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David Harris
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6fd32b6643
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-19 06:49:25 -08:00 |
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David Harris
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887cf935dc
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wallySynthAll.sh automates running all synthesis experiments without maxopt
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2023-11-19 06:49:07 -08:00 |
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David Harris
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b692c913c4
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Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile
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2023-11-18 20:56:50 -08:00 |
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David Harris
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acd8a63628
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Merge pull request #489 from ross144/main
fixes issue #487
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2023-11-18 19:22:33 -08:00 |
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