960 Commits

Author	SHA1	Message	Date
David Harris	3f3c20a38f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-21 14:04:02 -08:00
David Harris	b5f79c44f9	Reset STIMECMP to 0 to agree with ImperasDV	2023-11-21 13:43:51 -08:00
Rose Thompson	58d89cc347	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-11-21 10:48:05 -06:00
Rose Thompson	386cf3eb56	Merge pull request #493 from stineje/main ... marchid approved by RISC-V	2023-11-21 08:33:07 -08:00
James E. Stine	141cbd3f9f	Update marchid/mvendorid for CV-Wally	2023-11-21 09:23:02 -06:00
David Harris	d3ce683e06	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
David Harris	f89fd8a7fe	removed unused cache signals	2023-11-20 23:16:35 -08:00
Rose Thompson	1acc3951c8	More simplifications.	2023-11-21 00:19:24 -06:00
Rose Thompson	1d811b085c	More cleanup.	2023-11-21 00:14:59 -06:00
Rose Thompson	d2a747bf3d	cleanup.	2023-11-20 23:59:40 -06:00
Rose Thompson	70eb110a9c	More optimizations to simplify cmo logic.	2023-11-20 22:13:31 -06:00
Rose Thompson	52ac07ce8d	Removed the CMO_WRITEBACK state from the cache and unused signals.	2023-11-20 20:56:30 -06:00
Rose Thompson	667fe035c0	Simplified CMO.Zero fsm implementation slightly.	2023-11-20 17:01:43 -06:00
Rose Thompson	eed6f11df6	Merge branch 'main' of github.com:ross144/cvw	2023-11-20 11:29:45 -06:00
Rose Thompson	23e05cb8b2	Finally have the cbo way muxing controls reduced to something sane.	2023-11-20 11:28:03 -06:00
David Harris	8cb433cb66	Commented IROM preloading	2023-11-19 19:33:57 -08:00
David Harris	acd8a63628	Merge pull request #489 from ross144/main ... fixes issue #487	2023-11-18 19:22:33 -08:00
Jacob Pease	a1e7158bd9	Merge branch 'main' of github.com:openhwgroup/cvw	2023-11-18 19:20:48 -06:00
Jacob Pease	87e6a5ccf2	Updated ROM to preload bootloader from file and infer a block ram when building for FPGA.	2023-11-18 19:15:39 -06:00
Rose Thompson	8cbd3de413	Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.	2023-11-18 19:01:39 -06:00
David Harris	acc2db256f	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
David Harris	eef39bd495	Fixed typo in lsu parameter	2023-11-15 08:30:48 -08:00
David Harris	817ddbc7c5	Adjusted LSU misaligned buffer to fix synthesis warning	2023-11-15 08:19:50 -08:00
David Harris	98176665de	Fixed messed-up hazard.sv	2023-11-15 08:05:41 -08:00
naichewa	8ffce456bd	Merge branch 'spi' into main	2023-11-14 14:51:06 -08:00
naichewa	1ab7c926ea	Final Code Review	2023-11-14 13:44:59 -08:00
Rose Thompson	bf51948616	Merge pull request #474 from davidharrishmc/dev ... FP and synthesis cleanup	2023-11-14 12:03:01 -08:00
David Harris	8ba0336c6f	Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e	2023-11-14 11:01:58 -08:00
David Harris	a77bea9954	Merge pull request #472 from ross144/main ... Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building	2023-11-14 08:34:06 -08:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	a6995af91c	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
Rose Thompson	707b0c557c	Cleanup and optimization of Zicclsm.	2023-11-13 14:28:22 -06:00
Rose Thompson	cc7a0b211a	Cleanup.	2023-11-13 12:35:11 -06:00
David Harris	121f685fa2	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
David Harris	c44ae93e22	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:27 -08:00
David Harris	065f3f3f6d	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:14 -08:00
David Harris	571c7d3be4	Divider cleanup	2023-11-12 19:41:12 -08:00
David Harris	f437336540	Explained sqrt preshifting	2023-11-12 10:05:54 -08:00
David Harris	7c50b2c571	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
David Harris	002034845a	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
David Harris	6ac83c776e	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
David Harris	2bf5143163	Bug fixes related to size of fpdivsqrt bit count and number of cycles	2023-11-11 05:58:53 -08:00
David Harris	d5ba8fc5e6	fdivsqrt parameter cleanup	2023-11-10 18:33:08 -08:00
David Harris	3cae2385ab	Simplified out LOGRK parameter	2023-11-10 18:19:41 -08:00
David Harris	7d0d9dcebe	divider cleanup	2023-11-10 18:01:13 -08:00
David Harris	03864642a7	fdivsqrt cleanup	2023-11-10 16:42:32 -08:00
David Harris	c5b12b7331	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-10 16:40:54 -08:00
Rose Thompson	c8cca8dfb8	Simplification.	2023-11-10 18:39:36 -06:00
Rose Thompson	c0e02ae190	Found another bug in the RTL's Zicclsm alignment.	2023-11-10 18:26:55 -06:00
Rose Thompson	02ab9fe99c	Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.	2023-11-10 17:58:42 -06:00