Skylar Litz
bb8587e06f
update to match new filesystem organization
2022-03-26 21:28:32 +00:00
Kip Macsai-Goren
8cde06b886
added basic trap tests that do not pass regression yet. updated signature adresses
2022-03-25 22:57:41 +00:00
Ross Thompson
7099259ff7
I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
2022-03-25 13:10:31 -05:00
Ross Thompson
7a824eaae1
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
bbracker
b08066381a
fix multiple-context PLIC checkpoint generation
2022-03-25 01:02:22 +00:00
bbracker
150a7b234b
tabs vs spaces disagreement
2022-03-24 17:11:41 -07:00
bbracker
9f60256f22
1st attempt at multiple channel PLIC
2022-03-24 17:08:10 -07:00
Ross Thompson
58668812c1
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-23 14:10:38 -05:00
Katherine Parry
abdbc31d14
fixed typo in unpack.sv
2022-03-23 18:26:59 +00:00
Ross Thompson
f1787670d4
Cleanup in testbench-linux.sv.
2022-03-22 22:34:38 -05:00
Ross Thompson
6c9750c725
reverted temporary change to configs.
2022-03-22 22:31:34 -05:00
Katherine Parry
ead88fba55
fixed lint error in fpudivsqrtrecur.sv
2022-03-23 03:24:41 +00:00
Ross Thompson
6ab14d7302
Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
2022-03-22 22:04:06 -05:00
Ross Thompson
600a97982f
Reverted change to configuration which caused issue with lint.
2022-03-22 21:44:08 -05:00
Ross Thompson
c5be2cb1d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-22 21:28:50 -05:00
Ross Thompson
7fc128ba7c
added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
2022-03-22 21:28:34 -05:00
Katherine Parry
c3c764a171
unpack.sv cleanup
2022-03-23 01:53:37 +00:00
Ross Thompson
80d376877a
Added spoof of uart addresses +0x2 and +0x6.
2022-03-22 16:52:27 -05:00
Ross Thompson
cec7625d91
Added comment about needed fix to misaligned fault.
2022-03-22 16:52:07 -05:00
Katherine Parry
2042374102
FMA parameterized and FMA testbench reworked
2022-03-19 19:39:03 +00:00
Ross Thompson
d347de8c49
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616
cleanup of ram.sv
2022-03-11 18:09:22 -06:00
Ross Thompson
d68446cf92
Added new asserts to testbench.
2022-03-11 15:41:53 -06:00
Ross Thompson
e802deb4d6
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
81a2fbb6d2
mild cleanup.
2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5
atomic cleanup.
2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445
Name changes.
2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
5c16b65a16
simplified uncore's name for HWDATA.
2022-03-10 18:17:44 -06:00
Ross Thompson
543e10ab32
Moved subwordwrite to lsu directory.
2022-03-10 18:15:25 -06:00
Ross Thompson
54abd944e2
Simplified byte write enable logic.
2022-03-10 18:13:35 -06:00
Ross Thompson
50789f9ddd
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
f7df3a0666
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
83133f8c47
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
d5f524a15e
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
David Harris
b1340653cf
bit write update
2022-03-09 19:09:20 +00:00
David Harris
004853c312
Refactored SRAM bit write enable
2022-03-09 17:49:28 +00:00
David Harris
ba9320d822
Updated testbench to read expected flags
2022-03-09 13:58:17 +00:00
Ross Thompson
2a8a1cd191
Minor cleanup to interlockfsm.
2022-03-08 23:38:58 -06:00
Ross Thompson
ac9528b450
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-08 18:05:35 -06:00
Ross Thompson
ed32801cc1
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
534fd70f76
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
David Harris
5d0b9bab6e
Added more test cases and rounding modes to fma test generator
2022-03-08 23:29:29 +00:00
David Harris
582b943380
fixed setup.sh merge conflict
2022-03-08 23:21:06 +00:00
David Harris
cfa82efccc
fma16_testgen.c test cases
2022-03-08 23:18:18 +00:00
Ross Thompson
acd60218b8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
bbracker
51e68819c4
fix up PLIC and UART checkpointing
2022-03-07 23:48:47 -08:00
bbracker
c2ac18b5de
change testbench-linux.sv to use new shared location of disassembly files
2022-03-07 20:04:08 -08:00
David Harris
d2282d5e87
Checked in fma16_template.v
2022-03-06 13:29:35 +00:00
David Harris
9fd861a9ee
removed more old 64priv tests
2022-03-04 03:57:19 +00:00
bbracker
51f1a411dd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:12:00 +00:00
bbracker
1c5697874f
comment out nonfunctioning CSR-PERMISSIONS-M test
2022-03-04 00:11:55 +00:00
David Harris
63e9d846e4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:07:34 +00:00
David Harris
48705457d5
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
bbracker
efb5d1dbc0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-04 00:06:27 +00:00
bbracker
443dd40ea8
remove imperas32p tests
2022-03-04 00:06:18 +00:00
David Harris
545f569f78
Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
2022-03-03 15:38:08 +00:00
David Harris
080fef6436
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-02 23:47:16 +00:00
David Harris
8fbdbba81a
fma file fixes
2022-03-02 23:47:01 +00:00
bbracker
e28ca531e0
fix peripheral test and add it to regression
2022-03-02 23:44:39 +00:00
bbracker
be2f668867
but apparently QEMU doesn't show UXL in SSTATUS
2022-03-02 22:44:19 +00:00
bbracker
01e0f2f0d2
update SXL UXL bits in MSTATUS to match new QEMU trace
2022-03-02 22:15:57 +00:00
bbracker
c1290d493f
add CSRs to waveview
2022-03-02 18:31:10 +00:00
bbracker
d7b8c9d877
add rv32a tests to regression
2022-03-02 17:54:55 +00:00
bbracker
6c422cd357
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-03-02 17:46:40 +00:00
David Harris
3bea7bb431
removed imperas-riscv-tests
2022-03-02 17:28:20 +00:00
bbracker
5f5cc514b8
fix buildroot checkpointing and add it back to regression
2022-03-02 16:00:19 +00:00
bbracker
4f22a55dd4
add LRSC test and add wally64a to regression
2022-03-02 07:09:37 +00:00
David Harris
1661983345
FMA project ready to start
2022-03-01 20:58:08 +00:00
bbracker
41b3912abc
buildroot graphical sim bugfix
2022-03-01 03:24:23 +00:00
bbracker
04ace8c154
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
bbracker
d620fb4442
deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test
2022-03-01 00:37:46 +00:00
David Harris
f314e60dc8
Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath
2022-02-28 20:50:51 +00:00
David Harris
f0a7ae2bba
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
e108eb5195
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
David Harris
bb14dba9be
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
David Harris
046259cff8
Moved regression work directories to regression/wkdir to reduce clutter
2022-02-27 17:35:09 +00:00
David Harris
c7b5d32a72
Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior
2022-02-27 17:23:33 +00:00
David Harris
c6561d1e8b
Moved FMA back into source tree to facilitate synthesis
2022-02-27 15:41:41 +00:00
David Harris
eb0bbacd43
Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue
2022-02-27 15:12:10 +00:00
David Harris
274ecf13ad
Moved fma directory
2022-02-27 14:20:15 +00:00
David Harris
5a5142c14f
fma simulation infrastructure
2022-02-27 04:36:43 +00:00
David Harris
d917cc1379
fma passing multiply vectors
2022-02-27 04:36:01 +00:00
David Harris
8a55935456
simplified fma Makefile
2022-02-26 19:55:42 +00:00
David Harris
1852eccaab
Made softfloat.a a symlink
2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac
Added start of fma
2022-02-26 19:51:19 +00:00
David Harris
eda60a7691
Moved Softfloat / TestFloat
2022-02-26 19:17:32 +00:00
Ross Thompson
97d64201f7
Fixed bug with DAPageFault being wrong when HPTW writes not supported.
2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc
More spillsupport more structual.
2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
d331b9f29d
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
Ross Thompson
6a52f95cc8
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c
fix lint bugs in PLIC and UART
2022-02-22 05:04:18 +00:00
bbracker
a6047697c3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-22 04:27:50 +00:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
bbracker
e7934c585a
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
a6e83a2ca2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 12:46:22 -06:00
Ross Thompson
56fc6d0d7c
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
ushakya22
67780305ae
Moved order of reading a, b, and result from test vectors file so that result
...
matches up with inputs a and b
2022-02-21 17:28:11 +00:00
ushakya22
88060a74f5
- created new testbench file instead of having it at the bottom of the srt file
...
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench
Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
2022-02-21 16:24:50 +00:00
ushakya22
d1089163a9
- Created exponent divsion module
...
- top module includes exponent module now
Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
2022-02-21 16:13:30 +00:00
ushakya22
c6bd51a707
Changed Makefile to compile exptestgen instead of testgen
2022-02-21 16:08:45 +00:00
ushakya22
08d997d68b
reverted srt_standford back to original file pre modifications by Udeema
2022-02-21 16:08:09 +00:00
ushakya22
1495f6ac70
verilator lint for srt
2022-02-21 16:05:43 +00:00
ushakya22
5b83ad0929
Created test vector generation file for exponent and mantissa division
2022-02-21 16:04:41 +00:00
Ross Thompson
f48b12b089
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
cbf4395457
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
d1578d8356
added scratch register tests for 64 and 32 bits
2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
5bdb612567
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-21 00:34:54 +00:00
Ross Thompson
ae06785b9f
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
20a5798f43
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
6a0ffff05d
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
4113d64b19
added 32 bit pma tests to regression even though they've been working fo a while
2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
c3523dfa15
Added misa test for both 32 and 64 bits
2022-02-18 19:41:50 +00:00
Ross Thompson
6cd9d84e7f
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
ad237b3ce5
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
cbac34943c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
f3c7025ade
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
Skylar Litz
0c69d3291d
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
6c1383e2a0
added CSR permission and minfor to 32 bit tests
2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f
merged test macros in with 32 bit tests
2022-02-15 20:19:14 +00:00
David Harris
aa990be959
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Kip Macsai-Goren
9266bc382e
light cleanup for privileged tests
2022-02-15 17:06:16 +00:00
Ross Thompson
fcbb577f31
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
143eb0ae65
srt fixes
2022-02-14 18:40:27 +00:00
David Harris
3598e05998
srt batch files
2022-02-14 18:37:46 +00:00
ushakya22
3e2e9bc6a0
bring branch back into main
...
Merge branch 'srt_division_with_unpacker' into main
2022-02-14 18:25:34 +00:00
ushakya22
df561f8550
work in progress exponent handling
2022-02-14 18:24:29 +00:00
David Harris
caa4d83e57
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63
More cache cleanup.
2022-02-13 12:38:39 -06:00
ushakya22
a996a5e16c
Added unpacker into testbench for srt
2022-02-12 22:05:18 +00:00
David Harris
f5678e25db
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
b537df2651
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
b1cba4be2b
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
20456097cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
9ad4523b9d
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
f23817bf69
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a
Cache name clarifications.
2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154
More cache cleanup.
2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98
structural muxes.
2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05
More cache cleanup.
2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
327a05c9d8
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
Ross Thompson
01126535db
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d
Cleanup IFU.
2022-02-08 14:54:53 -06:00
