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1305 Commits

Author SHA1 Message Date
Katherine Parry
a4cd157f00 forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
e498d87c5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-15 20:17:08 +00:00
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
cturek
ec9536f983 Square root radix 2 working, does not work with division 2022-07-14 22:52:09 +00:00
cturek
9f18f6a203 Square root 2022-07-14 21:19:45 +00:00
cturek
38bbd19abf Six tests passing and a bunch of sizizing issues fixed 2022-07-14 19:38:27 +00:00
Katherine Parry
a0e9e93d4f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-14 18:16:13 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
cturek
f49c2a969f S and SM are updating but are not correct yet 2022-07-14 00:39:30 +00:00
Katherine Parry
e5a8ac2a44 renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
cturek
7629173b15 DIVLEN and counter updated for sqrt computation and rounding 2022-07-13 22:42:39 +00:00
Katherine Parry
7e163e22a3 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
77ea4e47cb removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
cturek
d57fb6f98a radix 4 files removed from srt and divlen modified for sqrt 2022-07-13 19:46:48 +00:00
cturek
9b7e63f482 Lint error fixed and added comments to preprocessing 2022-07-13 19:34:04 +00:00
cturek
81f396f885 Testbench accepts standard test vector files 2022-07-13 18:30:18 +00:00
cturek
11bb3f0a3e Test generation files in common format 2022-07-13 18:11:13 +00:00
cturek
110b762b55 Finalized sqrt, ready for debugging 2022-07-13 17:56:23 +00:00
cturek
31db938e7e Added adder input selection to on the fly converter 2022-07-13 17:47:27 +00:00
cturek
bb7e73abf0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-13 17:36:56 +00:00
Katherine Parry
26e39dd325 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
cturek
5c9f011561 little fix 2022-07-12 23:04:33 +00:00
cturek
ed9106128f Square root implemented 2022-07-12 22:45:54 +00:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
cturek
9d4acc9ddb C register and other various fixes 2022-07-12 22:18:56 +00:00
cturek
3483b92480 On the fly conversion for square root 2022-07-12 02:21:38 +00:00
Katherine Parry
5c0ecfa433 forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
DTowersM
191c7a2ee3 added some preliminary support for coremark XLEN=32, made sure rv64 not impacted 2022-07-11 21:13:09 +00:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
cturek
2dc074ea93 F Selection 2022-07-08 21:53:52 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
d10ad0e883 Removed testbench code that ignores mismatch on zero signatures 2022-07-08 09:17:31 +00:00
David Harris
c72e4d43d2 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
905b7ffc84 moved unsused division code again 2022-07-07 16:41:26 -07:00
cturek
b7e590ebb0 Sqrt exponents 2022-07-07 23:34:56 +00:00
Katherine Parry
5751d86f69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-07 16:29:44 -07:00
Katherine Parry
2bbde827e6 Revert "moved old divsqrt to unusedsrc" 
This reverts commit c9f5ae12ea.
 2022-07-07 16:29:17 -07:00
DTowersM
5a68ff9afb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-07 23:11:35 +00:00
DTowersM
d55833e4f3 new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory 2022-07-07 23:11:02 +00:00
Katherine Parry
c9f5ae12ea moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
cturek
b41a6f069b Seventeen Square Root Tests 2022-07-07 22:48:46 +00:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
cturek
89e17b6f3c Preprocessing for square root 2022-07-07 21:23:30 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
b7462ed6ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 15:51:33 +00:00
slmnemo
c5fd98ba99 sim-buildroot-batch now runs wally-pipelined-batch 
with option buildroot buildroot-no-trace to boot linux from step 0
 2022-07-06 18:06:43 -07:00
David Harris
6a030fc2a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:44:47 +00:00
DTowersM
47a990d9f1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD 2022-07-06 23:44:27 +00:00
DTowersM
1e8ccf3449 added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu 2022-07-06 23:43:57 +00:00
David Harris
08ae2db080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
cb33d2289b fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
9ef38145d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
a599084b88 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
846f12aa2e new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
01e6d69a67 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
cturek
e7ac99a683 Radix 2 Integer division working (without signs or remainder) 2022-07-05 21:34:49 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
d033659beb Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
e7fe7ad0c8 AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
4723ff559c Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
aa3dc8bfe1 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
4c48d71e4b removed delay in ahblite 2022-07-05 04:59:28 +00:00
David Harris
dab87811e9 Removed sig4 spurious message from testbench 2022-07-05 03:27:14 +00:00
David Harris
2b3038edf8 Added check to halt testbench on failing to find file 2022-07-05 02:28:59 +00:00
Katherine Parry
010a05f583 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
bde1c5eb1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
52dbc9f8be FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
575b73fa8c some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
slmnemo
67fd3be9d4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-29 13:40:15 -07:00
slmnemo
11956d0661 ./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000 2022-06-29 13:40:11 -07:00
Daniel Torres
a384a6465b reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished 2022-06-29 12:32:30 -07:00
Daniel Torres
50b9b4557c added changes to testbench, tests and riscof for additional riscof compatability 2022-06-29 12:23:40 -07:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
478a2e2a4b removed an adder out of early termination 2022-06-28 18:01:11 +00:00
slmnemo
448c9fdbb9 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
Katherine Parry
a3e46348c7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-28 00:16:36 +00:00
Katherine Parry
f2d05911ca very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
cturek
3a40c68549 Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work. 2022-06-27 23:55:21 +00:00
cturek
54938c7abf Added int tests 2022-06-27 21:44:06 +00:00
Katherine Parry
f25bb4a384 radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
2d5d1f4e8f radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
06f7f9b147 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
d16ae7c305 passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
913a381442 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
c1b4e7fd2c modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a65c0eb679 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
d058ec6329 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
45e918b02f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-24 01:09:53 +00:00
Katherine Parry
fc75fc633f division by zero added 2022-06-24 01:09:44 +00:00
slmnemo
51426ab71a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-23 16:51:51 -07:00
slmnemo
7c019ea074 Removed references to initialization files 2022-06-23 16:50:27 -07:00
Katherine Parry
86cdbd90e6 forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
97ded2cdd9 div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
d17596353b lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
b54d84195f added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
53b2487ead Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-23 14:39:59 -07:00
slmnemo
ded2631567 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
Katherine Parry
5133b08161 generate qsel4 in verilog 2022-06-23 21:38:04 +00:00
slmnemo
a77fb485db Added wally32periph to regression 2022-06-23 14:37:18 -07:00
David Harris
2c4b86c703 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
ceddc99ac9 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
James Stine
79bf543ba9 Update 2022-06-23 11:59:05 -05:00
James Stine
001e8e077d Add sqrt qlsc table generator 2022-06-23 11:46:44 -05:00
Katherine Parry
49067792dc fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
slmnemo
3e2afdf53b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 16:10:25 -07:00
slmnemo
10b6ff39a8 changed order of makefiles and fixed warnings when running makes 2022-06-21 16:10:18 -07:00
David Harris
2577b5c3a4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:56:02 +00:00
David Harris
3d5645d683 Trimmed lint-wally 2022-06-21 22:56:01 +00:00
slmnemo
d291387b81 added individual makes for arch and wally tests as well as memfiles to Makefile. run using make archtests/wallytests/memfiles 2022-06-21 15:54:24 -07:00
Katherine Parry
e9f5778e2a using memread for quotent select 2022-06-21 15:49:52 -07:00
Katherine Parry
c41391e228 removed rv64fp from lint 2022-06-21 15:48:47 -07:00
David Harris
8537b883d1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 22:45:28 +00:00
Daniel Torres
cf56a0d76a fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely 2022-06-21 15:39:04 -07:00
Madeleine Masser-Frye
0161683945 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
fe31ee92e8 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
James Stine
493d3b1ac0 Add hex output in bad but okay way 2022-06-21 15:07:24 -05:00
James Stine
8e177b02e4 Add MATLAB scripts for PD plot 2022-06-21 10:14:53 -05:00
slmnemo
2b2760f5bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
2b2ddbcc5e Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
edc15d6ef9 made fixes to radix-2 divider testbench - divider doesn't pass 2022-06-20 23:01:53 +00:00
Katherine Parry
5d5f79eb8f radix-4 divider passing tests 2022-06-20 22:56:08 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
James Stine
1108268557 Update C program for r=4 division by recurrence to match Table in EL 2022-06-20 11:32:40 -05:00
Daniel Torres
d077199608 embench and testbench now support running both O2 and Os build variations without overwriting one another 2022-06-17 21:15:42 -07:00
Daniel Torres
1ef5ed8005 arch tests now run on spike and sail and compare signatures during build 2022-06-17 20:53:15 -07:00
Daniel Torres
dcdd3702c3 removed old code from makefile, simplified code in testbench 2022-06-17 15:13:38 -07:00
Daniel Torres
3a5c02b44a arch bug fixes and testbench changes 2022-06-17 15:07:16 -07:00
David Harris
7e4988c2de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-17 15:45:24 +00:00
Katherine Parry
8425f8838d hopefully fixed lint error 2022-06-17 00:14:39 +00:00
Katherine Parry
93906b9457 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
e121dcd4af postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
c2493168b6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
76e30ed8ab cleanup, plots for paper 2022-06-15 18:28:36 +00:00
James Stine
d69a8f4077 Add back SV for integer division to use 8-bit CPA in qslc 2022-06-15 11:46:39 -05:00
James Stine
535a9a04ee Add r=4 C code 2022-06-15 11:44:09 -05:00
Katherine Parry
11b252a735 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
David Harris
ecd733942a Removed testbench.sv.bak 2022-06-14 22:04:38 +00:00
Katherine Parry
998876ce49 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
566001e07b fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
DTowersM
919c1818a8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
DTowersM
1f4d56ba32 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
8ea484a343 Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
b7a7ca6eac Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
eb41185a70 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:30:33 -07:00
David Harris
be65e8f862 Removed SRT testvectors from repo 2022-06-13 19:27:33 +00:00
slmnemo
915b8e2adb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
7b704f8db0 Merge branch 'cacheburstmode' into main. 
Cache burst mode is now working! It also uses the new RAM.
 2022-06-13 12:26:18 -07:00
slmnemo
98c07ce2c0 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
ccd16210bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
e9ef9a5cb8 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
3d715a098c Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
422bd2043f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
7cdf9cd4d3 added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
DTowersM
4bbe5eeecd simplified coremark 2022-06-10 19:15:17 +00:00
slmnemo
dc11066ff2 Passed Regression: Seems to work perfectly fine 2022-06-09 18:21:13 -07:00
slmnemo
ec7cdee0f3 Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
slmnemo
5a6eae214a ? 2022-06-09 17:50:47 -07:00
DTowersM
9e2d80764d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-10 00:38:07 +00:00
DTowersM
dd34f25ffd changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
slmnemo
3e8d3bae88 Changes made on 9th Jun 2022-06-09 17:33:51 -07:00
slmnemo
4ff105f18c Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c836f37a08 New RAM for further testing 2022-06-09 23:50:43 +00:00
stineje
470c0552f8 Update integer division for r4 and qslc_r4a2.c 2022-06-09 16:45:13 -05:00
David Harris
dd4fa7c682 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
0d04751c77 Fixed error when doing uncached accesses where HTRANS was always 2 2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. 2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye
0e64494e46 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a58a756076 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
11924bdd9b Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
e17ee3073e Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
315c2f0669 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
6402b2dec4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
6944996329 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
284e0395a0 Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42 Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
5240bd1c90 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
3c8eafc8ee Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
9e5ab4d378 Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
DTowersM
a190342b8a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 23:58:58 +00:00
DTowersM
02a424d65b modified testbench.sv- now works with coremark 2022-06-07 23:58:50 +00:00
DTowersM
e324db71b4 cleaned up the <begin_signature> code, now works for code bases larger than 0x10000000 2022-06-07 23:27:54 +00:00
slmnemo
6d36150c3d Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
DTowersM
df330961b8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-07 06:03:19 +00:00
DTowersM
590cf243bb added support for 64 bit rv tests 2022-06-07 06:02:23 +00:00
Katherine Parry
cfcaddf8aa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-06 16:06:54 +00:00
Katherine Parry
8fa0fc4229 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
slmnemo
7f70655113 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-03 18:56:29 -07:00
slmnemo
3fe78c9084 Fixed recurrent issue with testbench where it would never stop 2022-06-03 18:56:24 -07:00
cturek
afdfe770fc Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench. 2022-06-04 00:14:10 +00:00
DTowersM
caaf56cbf7 testbench now reads begin_signature addr from .objdump.addr instead of from tests.vh 2022-06-03 22:07:14 +00:00
Madeleine Masser-Frye
56a053fc3d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
31e9d0a41a added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
fd980fe9d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-03 15:34:27 +00:00
Katherine Parry
6b39b8c702 fixed compilation errors 2022-06-03 15:34:17 +00:00
slmnemo
9d1dfbdb50 Changed NO_SPOOFING from 0 to 1 in buildroot-no-trace to better facilitate wally booting linux without following QEMU's trace 2022-06-03 04:55:14 -07:00
Katherine Parry
8420b1e87c removed some debuging code accedentally pushed 2022-06-02 22:45:19 +00:00
Katherine Parry
6a4502e987 added rv64fpquad 2022-06-02 22:10:00 +00:00
Katherine Parry
cd8b2a2b98 added config rv64fpquad 2022-06-02 22:09:11 +00:00
David Harris
c74fec7fa6 renamed sim-fp to sim-testfloat 2022-06-02 15:05:29 -07:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
slmnemo
c8515001a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 12:54:08 -07:00
Katherine Parry
9a09ee3a35 fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
88454aa2ab Revert "parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do" 
This reverts commit 89c7438424.
 2022-06-02 12:45:21 -07:00
slmnemo
ad9e85beb9 Revert "Fixed buildroot by adding a second ." 
This reverts commit 8b27c1884e.
 2022-06-02 12:43:59 -07:00
slmnemo
65b8d0c32a Revert "Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py" 
This reverts commit e33ca59d46.
 2022-06-02 12:41:01 -07:00
slmnemo
0d650b2880 Revert "Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace" 
This reverts commit e4024eb503.
 2022-06-02 12:40:46 -07:00
David Harris
1d8bc2dc1b Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
154410a37f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-02 15:48:36 +00:00
David Harris
faa15b1f8d Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
197b588193 Cleaned up test cases in testbench 2022-06-02 08:44:28 -07:00
David Harris
c7ec9282fe Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
slmnemo
c16c5beef5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 02:52:03 +00:00
slmnemo
65961223f8 Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files 2022-06-02 02:51:51 +00:00
Katherine Parry
e42afbfb30 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
DTowersM
215f69a2ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-01 21:00:51 +00:00
DTowersM
d28b4cf602 added support for embench post processing to testbench.sv 2022-06-01 21:00:44 +00:00
Katherine Parry
dd19e55b8f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
446ad498aa Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
cturek
949f53695d Fixed typos 2022-06-01 00:07:36 +00:00
slmnemo
cf05fec9c7 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
a86c4d5ff3 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
9ad1a42886 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
475a84491e Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
f9533fea1a Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
0d0a9cba66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
aa7b0616e4 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
DTowersM
8903af3764 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 20:13:41 +00:00
DTowersM
525f6a6069 added testbench.sv support for embench tests, test output still WIP 2022-05-31 20:13:32 +00:00
DTowersM
0de54a01bf removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM 2022-05-31 20:10:56 +00:00
DTowersM
95df88ae70 added embench tests to tests.vh 2022-05-31 20:08:04 +00:00
Katherine Parry
f6ac33ce8a reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
4ed7933aa3 added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
788fe406b5 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
0cfe9e3373 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
950a17bef5 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
4a8d0be32c Reverted commit 60e3d7d81b 2022-05-28 04:00:01 -07:00
slmnemo
f18989e801 Revert Commit 6c61840045 2022-05-28 03:35:17 -07:00
slmnemo
60e3d7d81b Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name 2022-05-28 03:16:55 -07:00
slmnemo
6c61840045 Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do 2022-05-28 03:14:49 -07:00
slmnemo
f78fa3b9b9 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
b04e9ac1f6 fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4237bb7abd Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
9c58c63864 removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
a0ff98042c unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
95b506c5e0 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
1be91753fe moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
c6d79cd718 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bc17f883d4 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
847c7930c4 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
cturek
5a0889016c fixed sizing issues in expcalc 2022-05-26 22:35:17 +00:00
cturek
3301d7c52a Implemented on-the-fly conversion for unsigned numbers 2022-05-26 22:20:43 +00:00
Katherine Parry
3c04f1bdec Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 20:48:30 +00:00
Katherine Parry
9d281b2604 fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
80fc716cd7 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
DTowersM
6f0b5753ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 19:05:21 +00:00
DTowersM
7ffef6ccfa fixed indent spacing (cosmetic change) 2022-05-26 19:04:21 +00:00
cturek
4a4f153eef Set up the divider for on-the-fly conversion 2022-05-26 16:45:28 +00:00
slmnemo
08430a1e85 added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
e8d97f0826 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:41:04 -07:00
slmnemo
a2300f063d added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction 2022-05-25 17:40:57 -07:00
slmnemo
d1421b88ad Added line to testbench to prevent annoying burst sizes 2022-05-25 17:29:45 -07:00
slmnemo
cebf93cf9c idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
DTowersM
de60b15cfe Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-26 00:12:46 +00:00
slmnemo
012cb7439d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:11:03 -07:00
slmnemo
b5476204da see commit 9042cc3c 2022-05-25 17:10:59 -07:00
Katherine Parry
f3b28b988b added fcvt.sv 2022-05-26 00:10:51 +00:00
DTowersM
a1cda79cd5 Merge branch 'embench' into main 
embench contained the working makefiles for embench and is being merged into main as it working and done
 2022-05-26 00:10:50 +00:00
DTowersM
3f7eddbc89 working makefile for embench and removed testbench-f64 2022-05-26 00:08:18 +00:00
slmnemo
8422095a33 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-25 17:03:26 -07:00
slmnemo
4e5505f301 added logic to prevent cache line length from exceeding the max size of a burst. 2022-05-25 17:03:15 -07:00
cturek
c9845b96f4 Renamed variables for readability 2022-05-26 00:01:51 +00:00
cturek
51debfa186 Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
f35450207f single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
81a869c921 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
dd4997bd1b added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
slmnemo
0398aa02a0 fixed a comment spelling typo 2022-05-23 19:24:28 -07:00
Katherine Parry
576fe4ec24 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-23 23:11:41 +00:00
Katherine Parry
e5d2dfe94b added exponents to srt divider 2022-05-23 23:07:27 +00:00
David Harris
d78451e39c Checked in qst2.c from James 2022-05-23 20:26:05 +00:00
Ross Thompson
b70baed214 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
e2cf941a23 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
d91fd44ea5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
dbe4b4bafa added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
bcb4ebf888 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
c4f1a0362b Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
92a2ad02db Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
39a3bf5cdc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
b832a21b73 ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
slmnemo
e3a7e3e2f3 changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
Katherine Parry
5d34db85b2 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
0afac6904e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 18:31:56 -07:00
slmnemo
af0300c3d7 added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
slmnemo
11e703c8c0 fixed lint autofailing due to no log being produced in regression-wally 2022-05-19 18:30:59 -07:00
slmnemo
79c28d34dc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-19 17:51:45 -07:00
slmnemo
e4024eb503 Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace 2022-05-19 17:51:26 -07:00
slmnemo
e33ca59d46 Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py 2022-05-19 17:50:48 -07:00
slmnemo
8b27c1884e Fixed buildroot by adding a second . 2022-05-19 17:49:32 -07:00
slmnemo
89c7438424 parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do 2022-05-19 16:21:38 -07:00
Katherine Parry
ab1f088672 fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
6f2d8c24ad Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
bab7335bee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
d34f4a7c3c updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
c96f07ad75 added instructions to slack notifier 2022-05-18 16:50:31 -07:00
mmasserfrye
84422f3859 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
f8722f04f9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-18 16:10:36 +00:00
mmasserfrye
12c42cd507 adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
b853c4ba47 Updated fpga debugger. 2022-05-17 23:04:01 -05:00
slmnemo
23d6791b22 simplified make-tests.sh to run the current makefile in regression 2022-05-17 17:29:34 -07:00
slmnemo
82e68f2170 Revert "same as last breaking commit, testing if the bisect works to output a breaking commit." 
This reverts commit dcb485ec61.

gottem
 2022-05-17 17:26:33 -07:00
slmnemo
dcb485ec61 same as last breaking commit, testing if the bisect works to output a breaking commit. 2022-05-17 17:22:09 -07:00
slmnemo
b7d036f3d0 Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D." 
This reverts commit f970cc3ea9.

fixed it
 2022-05-17 17:05:11 -07:00
slmnemo
f970cc3ea9 broke it again but this time it doesn't compile due to a missing semicolon on Rs1D. 2022-05-17 17:03:16 -07:00
slmnemo
589bd0ca34 Revert "Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression" 
This reverts commit 4908f77cf9.

unbroke wally
 2022-05-17 16:57:29 -07:00
slmnemo
357d77d332 Revert "Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main"" 
This reverts commit 0e3099743c.

reverted the wrong commit
 2022-05-17 16:57:00 -07:00
slmnemo
0e3099743c Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 
This reverts commit 1c5a3de6d5, reversing
changes made to 1ff47888a7.

undid things
 2022-05-17 16:54:29 -07:00
slmnemo
4908f77cf9 Intentionally broke wally by setting datapath Rs1D to use bits 18:14 instead of 19:15 to test regression 2022-05-17 16:33:09 -07:00
slmnemo
1c5a3de6d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Added empty directory '/wkdir' to /pipelined/regression to avoid tests failing out of box due to the missing directory
 2022-05-17 20:32:53 +00:00
slmnemo
1ff47888a7 added wkdir in regression so regression runs out of box (assuming the old version of arch tests) 2022-05-17 20:32:38 +00:00
David Harris
a2280dadfd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 15:09:52 +00:00
David Harris
49f25bd03d Restored srt to working without exponent unit 2022-05-17 15:09:48 +00:00
mmasserfrye
2254a8218d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00