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1014 Commits

Author SHA1 Message Date
David Harris
e41a87be23 Restored counter events 2021-06-10 11:18:58 -04:00
David Harris
d386929c0e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-10 10:47:55 -04:00
David Harris
802238643a Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
bbracker
f272cd46d8 peripheral lint fixes 2021-06-10 10:19:10 -04:00
bbracker
d4aeb1c387 merge 2021-06-10 10:03:01 -04:00
bbracker
0321d74562 attempt to fix regression by adding PMP_ENTRIES to configs 2021-06-10 09:59:26 -04:00
bbracker
d9022551c2 buildroot progress -- able to mimic GDB output 2021-06-10 09:58:20 -04:00
bbracker
79e798a641 UART improved and added more reg read side effects 2021-06-10 09:53:48 -04:00
David Harris
3e8026dc21 Configurable number of performance counters 2021-06-10 09:41:26 -04:00
David Harris
75870a16d7 Restored PCCorrectE declaration in IFU 2021-06-09 21:09:16 -04:00
David Harris
0ffbd03139 More verilator fixes, but bpred is broken 2021-06-09 21:03:03 -04:00
David Harris
c7e57aeb1a removed verilator lint_off WIDTH 2021-06-09 21:01:44 -04:00
David Harris
01d6ca1e2a Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
2952550db7 More PMP entries 2021-06-08 15:33:06 -04:00
David Harris
90e5781471 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
a95a7a7b82 working version with new mmu comments, old boottim values 2021-06-08 15:20:25 -04:00
Kip Macsai-Goren
2155cb2e91 merge of reverted main into up to date main 2021-06-08 14:57:43 -04:00
Kip Macsai-Goren
361c71c5e9 reverted to working version with new mmu comments 2021-06-08 14:56:00 -04:00
David Harris
b613f46c2d Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
aab7bd94f7 Merge small mmu changes into main 2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
d6f47d5917 making mmu branch line up with main 2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
e209dbcf50 some cleanup of signals, not done yet 2021-06-08 13:39:32 -04:00
bbracker
cc91c774a6 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
e7e4105931 * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
49515245d9 remove redundant decodes, fixed mmu logic ins/outs 2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
1e174a8244 got rid of some underscores in filenames, modules 2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
c96695b1b6 implemented simpler page mixers, cleaned up a bit 2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
b27abc53e8 began updating cam line to reduce muxes, confusion 2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
6a63ad04d2 regression working partially done page mask 2021-06-07 17:02:31 -04:00
David Harris
9efbffdee5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-07 16:14:13 -04:00
David Harris
43a690dc42 Simplified superpage matching 2021-06-07 16:11:28 -04:00
Katherine Parry
0acf665a8b lint is clean 2021-06-07 14:22:54 -04:00
bbracker
28c6d60150 temporarily removing buildroot from regression until it is regenerated 2021-06-07 13:20:50 -04:00
David Harris
2ae5ca19b5 Continued merge 2021-06-07 12:49:47 -04:00
David Harris
ff62000e2c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
David Harris
dc0b19dfaa Merge difficulties 2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux 2021-06-07 09:46:52 -04:00
Katherine Parry
75a6097467 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
49200bd922 Cleaned up some unused signals 2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
22e8e06ac7 moved privilege dfinitions into wally-constants, upgraded relevant includes 2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
037aa6fa89 Merge branch 'mmu' into main 
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
 2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
3493027bf5 added shared constants file list of includes 2021-06-04 17:05:47 -04:00
Kip Macsai-Goren
1ae529c450 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
Ross Thompson
41a1e6112a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-04 15:16:39 -05:00
Ross Thompson
7406e33b61 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
191f7e61fd Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Ross Thompson
e0d0fdd708 Cleaned up the I-Cache memory. 2021-06-04 13:36:06 -05:00
Katherine Parry
fc65aedbd6 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
fdef8df76b Reorganized the icache names. 2021-06-04 12:53:42 -05:00
Ross Thompson
7c44f19925 Relocated the icache to the cache directoy. 2021-06-04 12:23:46 -05:00
David Harris
a26bf37be8 Started MMU 2021-06-04 11:59:14 -04:00
David Harris
4f71964529 Fixed RV32 MMU constants 2021-06-04 09:15:42 -04:00
David Harris
0674f5506e moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
8fb2ee6e86 added support for sv48 and some docs on how to use these files 2021-06-03 14:32:12 -04:00
Kip Macsai-Goren
1ea9b94cf1 added tests for SV48 and translation off with vmem 2021-06-03 14:28:52 -04:00
bbracker
ad3b103a86 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-03 10:03:26 -04:00
bbracker
4e765ee1c5 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
Ross Thompson
e50a1ef5e4 Fixed a few lint errors, 
clock gater was wrong,
missing signal definitions in branch predictor.
 2021-06-02 09:33:24 -05:00
bbracker
a683dd7fde Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-02 10:03:23 -04:00
bbracker
2c77a13c08 fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
5187574e8a implemented Sv48. 2021-06-01 17:50:37 -04:00
Kip Macsai-Goren
40cfa86935 Edited and added constants to support SV48 2021-06-01 17:49:45 -04:00
James E. Stine
eba7ce64f5 delete div.bak 2021-06-01 17:39:54 -04:00
Ross Thompson
babcea195a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 15:20:37 -05:00
Ross Thompson
0670c57fd2 The clock gater was not implemented correctly. Now it is level sensitive to a low clock. 2021-06-01 15:05:22 -05:00
James E. Stine
564d7c4adb Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00
James E. Stine
2eeb12c674 Updates to muldiv.sv for 32-bit div/rem 2021-06-01 15:31:07 -04:00
Ross Thompson
fe22fd2db8 added clock gater to floating point divider to speed up simulation time. 2021-06-01 13:46:21 -05:00
Ross Thompson
7f1653f073 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 12:42:21 -05:00
Ross Thompson
997c13a521 Forgot to include the new gshare predictor file. 2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
fac2431add Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-01 13:20:39 -04:00
Ross Thompson
ab509614bb Changed to bp config to use gshare. 2021-06-01 12:14:58 -05:00
Ross Thompson
89ad4477e4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-01 11:33:12 -05:00
Ross Thompson
857f59ab5c Now have global history working correctly. 2021-06-01 10:57:43 -05:00
James E. Stine
ddbdd0d5a2 Modify muldiv.sv to handle W instructions for 64-bits 2021-05-31 23:27:42 -04:00
Ross Thompson
f6c88666cf may have fixed the global branch history predictor. 
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
 2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
0fe63282f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-31 11:01:15 -04:00
James E. Stine
46a232b862 Cosmetic changes on integer divider 2021-05-31 09:16:30 -04:00
James E. Stine
9954d16fc9 Add enhancements to integer divider including: 
- better comments
  - optimize FSM to end earlier
  - passes for 32-bit or 64-bit depending on parameter to intdiv

Left div.bak in just in case have to revert back to original for now.
 2021-05-31 09:12:21 -04:00
James E. Stine
12c34c25f3 Modify elements of generics for LZD and shifter wrote for integer 
divider.
 2021-05-31 08:36:19 -04:00
bbracker
39ae743543 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
690815ca51 made priority encoder parameterizable 2021-05-28 18:09:28 -04:00
Ross Thompson
8a035104ac It's a bit sloppy, but the global history predictor is working correctly now. 
There were two major bugs with the predictor.
First the update mechanism was completely wrong.  The PHT is updated with the GHR that was used to lookup the prediction.  PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted.  This is important so that back to back branches' GHRs are not the same.  The must be different to avoid aliasing.  Speculation of the GHR update allows them to be different.  On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed.  Updates to follow.
 2021-05-27 23:06:28 -05:00
Katherine Parry
778ba6bbf5 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
1459d840ed All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
309e6c3dc1 FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
James E. Stine
bb99480fca delete old file for FPregfile 2021-05-26 09:13:09 -05:00
James E. Stine
77260643eb Add regression test for fpadd 2021-05-26 09:12:37 -05:00
Katherine Parry
e7190b0690 renamed top level FPU wires 2021-05-25 20:04:34 -04:00
Kip Macsai-Goren
45e7628e90 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-25 15:28:19 -04:00
Ross Thompson
fec40a1b75 fixed bug with icache miss spill fsm branch. 2021-05-25 14:26:22 -05:00
James E. Stine
bb5404e14a Update FPregfile to use more compact code and better structure for ease in reading 2021-05-25 13:21:59 -05:00
Ross Thompson
063e458ff0 Merge remote-tracking branch 'refs/remotes/origin/main' into main 2021-05-24 23:25:36 -05:00
Ross Thompson
16e037b8e9 Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF. 2021-05-24 23:24:54 -05:00
Kip Macsai-Goren
8ae43a15d4 partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields 2021-05-24 20:59:26 -04:00
James E. Stine
c4f3f2f783 Minor cosmetic elements on div.sv 2021-05-24 19:30:28 -05:00
James E. Stine
295263e122 Mod for DIV/REM instruction and update to div.sv unit 2021-05-24 19:29:13 -05:00
bbracker
f755827c90 slightly more path independence for using verilator 2021-05-24 18:11:56 -04:00
Ross Thompson
c5310e85c1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-24 14:28:41 -05:00
Katherine Parry
90d5fdba04 FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Ross Thompson
65632cb7c9 Fixed minor bug in instruction class decoding. 2021-05-24 13:41:14 -05:00
Ross Thompson
72f77656a3 Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). 2021-05-24 12:37:16 -05:00
Ross Thompson
8bf411c640 Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
James E. Stine
6f38b7633c Update header for FPadd 2021-05-24 08:28:16 -05:00
Katherine Parry
70968a4ec3 FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
bbracker
846553ac7d improved PLIC test organization 2021-05-21 15:13:02 -04:00
James E. Stine
e70136ec78 Minor testbench updates to rv64icfd 2021-05-21 09:41:21 -05:00
James E. Stine
23769e36a5 Update to testbench-imperase for rv64icfd 2021-05-21 09:28:44 -05:00
James E. Stine
fed3b30557 Update to FLD/FSD testbench 2021-05-21 09:26:55 -05:00
James E. Stine
c89d3e01bb Update to rv64icfd wally-config to run through FP tests 2021-05-21 09:22:17 -05:00
Katherine Parry
4db7f3065c FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
06af239e6c FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
1d3db5ead5 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
bbracker
bf6337f2f7 plic implementation optimizations 2021-05-19 18:10:48 +00:00
bbracker
979a9bf037 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
304e70d3ae Update rv64icfd batch script 2021-05-18 16:01:53 -05:00
James E. Stine
44dc665fc5 Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
bbracker
e4d51ebef5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-18 14:33:40 -04:00
bbracker
c495fc71f1 changed lint script to use absolute path for verilator because cron jobs stink at using paths 2021-05-18 14:33:22 -04:00
David Harris
26531f2634 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
David Harris
5da159d17e Removed rv64wally 2021-05-18 14:08:46 -04:00
David Harris
4d264c6f61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/regression/vish_stacktrace.vstf
 2021-05-18 14:01:19 -04:00
Katherine Parry
9464c9022d floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
bbracker
f00eb22700 fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
e4c90f503a regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
David Harris
9901f54b15 Deleted vish_stacktrace 2021-05-17 18:39:01 -04:00
James E. Stine
e808b06b82 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg
b818ce608a commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
James E. Stine
5506efc115 Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
James E. Stine
3d3e3434f6 Cleanup of regression 2021-05-17 16:58:15 -05:00
James E. Stine
daf780b9c2 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
James E. Stine
865b3ee219 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
b9e099d53c Fix comment 2021-05-14 08:06:07 -04:00
Thomas Fleming
6aa04af38d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-14 07:40:08 -04:00
Thomas Fleming
ea4e76938e Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Thomas Fleming
e27bc1cbf7 Clean up MMU code 2021-05-14 07:12:32 -04:00
Elizabeth Hedenberg
170f072b52 pushing coremark to main branch 2021-05-11 21:33:39 -04:00
Jarred Allen
041149eaf7 Minor fixes in regression 2021-05-09 13:57:09 -04:00
Jarred Allen
c7f400262c Fix bug in regression script 2021-05-06 12:56:57 -04:00
Domenico Ottolia
e3624ab2e6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 20:22:31 -04:00
Domenico Ottolia
88ab07d456 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
Jarred Allen
be029ba02c Clean up regression script and document it 2021-05-04 18:58:59 -04:00
ushakya22
682bc7b58e Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Thomas Fleming
1ec6ad14f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 15:22:21 -04:00
bbracker
8a7fc959eb small synthesis fixes 2021-05-04 15:21:01 -04:00
Thomas Fleming
19ac77d3fa Fix compiler warning in PMP checker 2021-05-04 15:18:08 -04:00
Domenico Ottolia
8398e653dd Re-add medeleg tests to testbench 2021-05-04 14:42:20 -04:00
Ross Thompson
a03a63a5c7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 13:04:20 -05:00
Ross Thompson
21acc45121 Fixed synthesis bug with icache valid bit. 2021-05-04 13:03:08 -05:00
ushakya22
2e225bd756 Updated CSR tests 2021-05-04 13:48:47 -04:00
Ross Thompson
52e4c49bbb Fixed icache pcmux control for handling miss spill miss. 2021-05-04 11:05:01 -05:00
Thomas Fleming
44ea58b771 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 03:14:38 -04:00
Thomas Fleming
3a3c88f5b1 Fix bug in PMP checker 
Now we only enforce PMP regions if at least one is non-null
 2021-05-04 03:14:07 -04:00
ushakya22
46f20745d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 02:22:17 -04:00
ushakya22
b805b98a8c Added MIE tests to testbench 2021-05-04 02:22:01 -04:00
Thomas Fleming
c9e5af30fa Disable PMP checker to fix test loops 
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
 2021-05-04 01:56:05 -04:00
Domenico Ottolia
1673ad6e27 Minor tweaks to mcause & scause tests 2021-05-04 01:33:49 -04:00
David Harris
45b0af497c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-04 01:19:57 -04:00
David Harris
d68fe44446 Fixed testbench to produce error when signature.output doesn't exist 2021-05-04 01:19:44 -04:00
Thomas Fleming
41a19153cc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 01:14:13 -04:00
Domenico Ottolia
67c7bfe34d Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE 2021-05-04 01:04:12 -04:00
Domenico Ottolia
973f32da47 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
a3b5ae9742 Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
ad40464557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
803a69efe6 Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
c0f054556c Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Domenico Ottolia
2669a6a0db Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
4d70e22a6a Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
997c9ad5c0 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
780ad3eaf4 working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
c5a306426a finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
b7159652f6 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
968994c04a updated pipeline tests 2021-05-03 22:07:36 -04:00
Thomas Fleming
0254ca7bf6 Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
David Harris
afd6153044 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
d07a7fd0f8 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
David Harris
93466a0b2a Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
e265aa4d41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:37:56 -04:00
David Harris
58ce0fbbcc Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
2d1d929485 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
2a33673e3c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
463ba1a2be coremark directory changes 2021-05-03 19:35:06 -04:00
David Harris
b66c7b81de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:29:01 -04:00
David Harris
233726e8d8 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
Ross Thompson
baf29454f1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:57:36 -05:00
Domenico Ottolia
0f10d577d2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:56:05 -04:00
Ross Thompson
82b4d42f32 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:56:00 -05:00
Ross Thompson
7f38056879 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Domenico Ottolia
5ab86a690b Fix bug that caused stvec to get the wrong value 2021-05-03 17:54:57 -04:00
Thomas Fleming
ba1afec621 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Thomas Fleming
eda5a267ee Implement PMP checker and revise PMA checker 2021-05-03 17:37:42 -04:00
Thomas Fleming
8dce32fd22 Remove remnants of InstrReadC 2021-05-03 17:36:25 -04:00
Jarred Allen
7d509252a7 Add lint to regression 2021-05-03 17:32:05 -04:00
Ross Thompson
e145670b15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 14:53:54 -05:00
Ross Thompson
cdb602c9ce Removed combinational loops between icache and PMA checker. 2021-05-03 14:51:25 -05:00
Ross Thompson
19a93345b5 Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
David Harris
d7438929d4 Extended maximum signature length to 1M 2021-05-03 15:29:20 -04:00
Katherine Parry
ff5a809c26 fpu warnings fixed/commented 2021-05-03 19:17:09 +00:00
Thomas Fleming
cfe64e7c24 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Ross Thompson
a54c231489 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00