David Harris
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d627512d2b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-25 20:12:55 -08:00 |
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Ross Thompson
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4f436dc7f0
|
Added missing assignment for no branch predictor mode.
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2022-12-24 17:08:29 -06:00 |
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David Harris
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0cc2b0fcd2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-24 12:24:38 -08:00 |
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Ross Thompson
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0d6ce1d459
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Fixed bug with the performance counters not updating.
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2022-12-24 14:24:17 -06:00 |
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David Harris
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10af4e4353
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ALU cleanup
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2022-12-24 07:18:35 -08:00 |
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cturek
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cc6f219bdd
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Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.
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2022-12-24 06:46:52 +00:00 |
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Ross Thompson
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b0d6c9616e
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Minor optimizations.
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2022-12-23 20:11:36 -06:00 |
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Ross Thompson
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6e9d1eb180
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-23 19:51:23 -06:00 |
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Katherine Parry
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4b50ffac91
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reworked negitive sticky bit handeling in fma
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2022-12-23 17:01:34 -06:00 |
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Ross Thompson
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6f9e21d61b
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Improved comment.
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2022-12-23 15:13:15 -06:00 |
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Ross Thompson
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a2de53aeeb
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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Ross Thompson
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fe9361de34
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Removed XEnE, YEnE, and ZEnE from forward logic.
Cleanup comments.
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2022-12-23 14:27:03 -06:00 |
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Ross Thompson
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af9afafdae
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Cleanup floating point hazard logic.
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2022-12-23 14:21:47 -06:00 |
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Ross Thompson
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b4c7998ded
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DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
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2022-12-23 12:47:18 -06:00 |
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Ross Thompson
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f6f66cb79e
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Removed ZForwardEnE and replaced with ZEnE.
Similar for YForwardEnE.
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2022-12-23 12:27:51 -06:00 |
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Ross Thompson
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ca67e5588d
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Removed unnecessary stall when MatchDE was driven 1 by RdE == 0.
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2022-12-23 11:45:42 -06:00 |
|
David Harris
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f038494760
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Commented out fdiv early termination - broke fsqrt test
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2022-12-23 00:58:55 -08:00 |
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David Harris
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e061bacc9d
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Fixed early termination on fdivsqrt
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2022-12-23 00:53:55 -08:00 |
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David Harris
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0505f1fd37
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Moved InstrValidNotFLushed to csr including InstrValidM
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2022-12-23 00:27:44 -08:00 |
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David Harris
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3b1fe78bdc
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Removed unused StallW from CSRs
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2022-12-23 00:21:36 -08:00 |
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David Harris
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9e21358d75
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Removed unused signals from FPU
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2022-12-23 00:18:39 -08:00 |
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David Harris
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0a7ed944a5
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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56312cd0a6
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Clean up unused FPU signals
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2022-12-22 23:53:09 -08:00 |
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David Harris
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4d509f94ec
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FDIV merge
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2022-12-22 23:03:03 -08:00 |
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David Harris
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2d72bed1f4
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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Ross Thompson
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98b824c4c4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-22 22:51:33 -06:00 |
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Ross Thompson
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2cc4d66ded
|
Renamed IFU and LSU stalls.
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2022-12-22 21:56:33 -06:00 |
|
Ross Thompson
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03021765a6
|
The LSU is properly using FlushW rather than TrapM.
|
2022-12-22 21:47:34 -06:00 |
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Ross Thompson
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3b791b768a
|
Success we've replaced TrapM with FlushD in the IFU.
|
2022-12-22 21:36:49 -06:00 |
|
Ross Thompson
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e0e92952c3
|
Partial cleanup for BP.
|
2022-12-22 20:33:38 -06:00 |
|
Ross Thompson
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206bc7daa6
|
Closing in on icache flushed by FlushD rather than TrapM.
|
2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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b1475df5e1
|
Wavefile updates.
|
2022-12-22 19:45:02 -06:00 |
|
Kip Macsai-Goren
|
a768d70093
|
Added status.tvm bit test that passes make and regression
|
2022-12-22 14:43:22 -08:00 |
|
Ross Thompson
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41fe876e7a
|
First pass at resolving ifu flush on trap rather than FlushD.
|
2022-12-22 15:53:06 -06:00 |
|
David Harris
|
d4bedca1bf
|
Code cleanup
|
2022-12-22 10:04:50 -08:00 |
|
cturek
|
ccbad67497
|
Added negative-result int diviison support in U and UM registers. 13 tests pass!
|
2022-12-22 16:25:37 +00:00 |
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cturek
|
1b7ed72ece
|
Moved swap from qslc to otfc
|
2022-12-22 15:44:50 +00:00 |
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cturek
|
3574bedb08
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-22 05:45:00 +00:00 |
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cturek
|
80ca75e216
|
Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
|
2022-12-22 05:44:55 +00:00 |
|
David Harris
|
c42967f5c6
|
XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-21 20:39:38 -08:00 |
|
Ross Thompson
|
c8c73f47d2
|
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
|
2022-12-21 22:13:05 -06:00 |
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cturek
|
0b4d81bd4a
|
worked out some bugs with int div cycles
|
2022-12-22 02:22:01 +00:00 |
|
cturek
|
c3fdc0ab23
|
Renamed signals to E and M stages, forwarded preprocessed n to fsm
|
2022-12-22 00:43:27 +00:00 |
|
Ross Thompson
|
84f8d9953f
|
Updated cache fsm names to match book.
|
2022-12-21 16:49:53 -06:00 |
|
Ross Thompson
|
d72cf65809
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-21 16:13:09 -06:00 |
|
Ross Thompson
|
e7a44d8975
|
Changed GatedStallF to GatedStallD.
|
2022-12-21 16:12:55 -06:00 |
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David Harris
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d0a3e939e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-21 14:12:25 -08:00 |
|
David Harris
|
8bc753a291
|
Added assertion about atomics needing caches
|
2022-12-21 13:57:28 -08:00 |
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cturek
|
0c30ecf86d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-21 20:41:38 +00:00 |
|
David Harris
|
6d46261350
|
comment cleanup
|
2022-12-21 12:39:09 -08:00 |
|
David Harris
|
c7f3aae084
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
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cturek
|
ab71962dc0
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-12-21 19:35:57 +00:00 |
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cturek
|
c479b9f112
|
fixed normshift calculations
|
2022-12-21 19:35:47 +00:00 |
|
David Harris
|
5ef3a1d371
|
git push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-21 11:31:27 -08:00 |
|
David Harris
|
e327d70cdc
|
Removed unused FPU signals
|
2022-12-21 11:31:22 -08:00 |
|
Ross Thompson
|
c3b43b2fac
|
Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
|
2022-12-21 13:16:09 -06:00 |
|
Ross Thompson
|
0b4186f1e8
|
Vectored interrupts now require 64 byte alignment.
Eliminates adder.
|
2022-12-21 12:05:49 -06:00 |
|
Ross Thompson
|
91f948a91c
|
The optimzied PC+2/4 logic still hanges on wally32priv.
|
2022-12-21 09:19:34 -06:00 |
|
Ross Thompson
|
6858b7568c
|
Renamed PCPlusUpperF to PCPlus4F.
|
2022-12-21 09:18:30 -06:00 |
|
Ross Thompson
|
3d95aa3423
|
Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
|
2022-12-21 09:18:00 -06:00 |
|
Ross Thompson
|
ac94b55e74
|
Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0.
Switched to even simplier PC+2/4 logic.
|
2022-12-21 09:00:09 -06:00 |
|
Ross Thompson
|
a02b40cf02
|
Changes to wave file.
|
2022-12-21 08:41:47 -06:00 |
|
Ross Thompson
|
fe723af1af
|
Comments about PC+2/4.
|
2022-12-21 08:35:43 -06:00 |
|
David Harris
|
5d91b3044f
|
Clean up vecgtored interrupts
|
2022-12-20 16:53:09 -08:00 |
|
David Harris
|
dd0a02f0c8
|
Converted tvecmux to structural
|
2022-12-20 16:24:04 -08:00 |
|
Ross Thompson
|
f860440361
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 18:09:37 -06:00 |
|
Ross Thompson
|
80be2e7be5
|
privileged pc mux cleanup.
|
2022-12-20 18:05:44 -06:00 |
|
Ross Thompson
|
97593e8a6f
|
Moved privileged pc logic into privileged unit.
|
2022-12-20 17:55:45 -06:00 |
|
David Harris
|
8f640f050f
|
IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI
|
2022-12-20 15:38:30 -08:00 |
|
Ross Thompson
|
35ad49502f
|
Implement FENCE.I as NOP when ZIFENCEI is not supported.
|
2022-12-20 17:34:11 -06:00 |
|
Ross Thompson
|
0dc09ac22d
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 17:11:35 -06:00 |
|
Ross Thompson
|
65cbff9283
|
Changed long names of vectored pcm signals.
|
2022-12-20 17:01:20 -06:00 |
|
David Harris
|
f3e9950317
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-20 14:43:33 -08:00 |
|
David Harris
|
e7702e48b7
|
FPU remove unused signals
|
2022-12-20 14:43:30 -08:00 |
|
Ross Thompson
|
6f543d01b7
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 16:36:44 -06:00 |
|
Ross Thompson
|
8029b12f2a
|
Renumbered bits for PCPlusUpper.
|
2022-12-20 16:33:49 -06:00 |
|
David Harris
|
caef1a6997
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-20 11:23:53 -08:00 |
|
David Harris
|
f0ef5caf32
|
Memory cleanup
|
2022-12-20 11:22:26 -08:00 |
|
Ross Thompson
|
c4901450c4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
|
2022-12-20 12:58:59 -06:00 |
|
Ross Thompson
|
684d260005
|
Reorganized IFU PCNextF logic.
|
2022-12-20 12:58:54 -06:00 |
|
David Harris
|
e74d47bcb4
|
Renamed renamed sram to ram
|
2022-12-20 08:36:45 -08:00 |
|
David Harris
|
16f3c25cb7
|
sram1p1rw cleanup
|
2022-12-20 02:57:51 -08:00 |
|
David Harris
|
08234cb1c7
|
Remoed unused bram modules
|
2022-12-20 02:40:45 -08:00 |
|
David Harris
|
2c46f22be5
|
Renamed SRAM2P1R1W to lower case
|
2022-12-20 02:09:55 -08:00 |
|
David Harris
|
54e856c4f5
|
Renamed SRAM2P1R1W to lower case
|
2022-12-20 02:09:36 -08:00 |
|
David Harris
|
caf457106a
|
Replaced || and && with single ops
|
2022-12-20 01:33:35 -08:00 |
|
Ross Thompson
|
dedc08bd42
|
several options for pcnextf on fence.i
|
2022-12-19 23:33:12 -06:00 |
|
Ross Thompson
|
2df18cc758
|
More bp/ifu pcmux cleanup.
|
2022-12-19 23:16:58 -06:00 |
|
Ross Thompson
|
565585b35a
|
Moved more muxes inside bp.
|
2022-12-19 22:51:55 -06:00 |
|
Ross Thompson
|
d8ee0ea59d
|
Begin cleanup of ifu. partial move of pc muxes inside bp.
|
2022-12-19 22:46:11 -06:00 |
|
David Harris
|
e4579f3e9b
|
Removed CSR support from rv32i
|
2022-12-19 16:15:12 -08:00 |
|
David Harris
|
9fea16fd20
|
Simplified InstrRawD register
|
2022-12-19 15:18:42 -08:00 |
|
David Harris
|
a4da3f30e1
|
Explained hazard causes
|
2022-12-19 09:41:41 -08:00 |
|
David Harris
|
67763dbeec
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-12-19 09:09:57 -08:00 |
|
David Harris
|
3172dfd6a9
|
Properly decode fcvtint to prevent unnecessary stalls
|
2022-12-19 09:09:48 -08:00 |
|
Ross Thompson
|
159eda85f0
|
Renamed FStallD to FPUStallD.
|
2022-12-19 09:28:45 -06:00 |
|
Alessandro Maiuolo
|
5a82898649
|
Added NumZeroE, AZeroM, and BZeroM
|
2022-12-18 20:02:40 -08:00 |
|
Alessandro Maiuolo
|
2989782fe6
|
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
|
2022-12-18 19:04:36 -08:00 |
|
Ross Thompson
|
4f56e6ff5d
|
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
|
2022-12-18 18:30:35 -06:00 |
|
Ross Thompson
|
376b01fcb8
|
Attempted to make a cache test.
|
2022-12-18 17:15:08 -06:00 |
|