Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
4,333 Commits 14 Branches 1 Tag 31 MiB
849d6d4297
Commit Graph

1008 Commits

Author SHA1 Message Date
David Harris
8cbdbb1c38 lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
d507bb3d70 busfsm simplified 2022-08-25 18:36:53 -07:00
David Harris
dc52f55aa6 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
50826c0b61 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
7cbca2dd22 Removed UncachedBusRead and UncachedBusWrite 2022-08-25 18:24:39 -07:00
David Harris
845807a329 Restored ahbtranstype 2022-08-25 18:22:26 -07:00
David Harris
4ab678ed48 Removed ahbtranstype 2022-08-25 18:21:45 -07:00
David Harris
f405a191af Removed WordCountFlag 2022-08-25 18:21:18 -07:00
David Harris
db7698202d Removed UncachedAccess 2022-08-25 18:20:52 -07:00
David Harris
7801ed48b3 Removed UncachedRW 2022-08-25 18:19:41 -07:00
David Harris
bb4ae908db Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
85b5587678 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
555083b0c3 Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
b982db5bd5 Removed STATE_BUS_FETCH and STATE_BUS_WRITE 2022-08-25 18:12:09 -07:00
David Harris
de9ec7cc2e Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
fb5ddc476c Removed CountEn 2022-08-25 18:05:44 -07:00
David Harris
7eae6765df Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
73419f0d41 Added buscachefsm for system with bus and cache 2022-08-25 18:01:01 -07:00
David Harris
0b918d6916 Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
5c1934208a Simplified swbytemask 2022-08-25 17:32:16 -07:00
David Harris
352bf88ac0 FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
David Harris
b96942e84c Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
Ross Thompson
109bcd470e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
Ross Thompson
e70c90d351 Finally resolved the issues with the rv32ic and rv64ic configurations. 2022-08-25 16:00:55 -05:00
Ross Thompson
ad3e632119 Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
David Harris
6222e15946 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
32f86b1b6b Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
David Harris
f782fe9367 Fixed brom name 2022-08-25 12:48:00 -07:00
Ross Thompson
bbf668e460 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:45:02 -05:00
David Harris
5b3c68fe74 ahblite cleanup 2022-08-25 12:44:25 -07:00
Ross Thompson
502eb0f5d1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:40:52 -05:00
David Harris
d7be94fab2 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
7a129af9ad Removed M sufix from busdp signals 2022-08-25 11:13:01 -07:00
David Harris
84ba62a04c Renamed LSUFunct3M to Funct3 in busdp 2022-08-25 11:08:12 -07:00
David Harris
78618f5fc0 Renaming LSU signals from busdp 2022-08-25 11:05:10 -07:00
David Harris
cd02c894df renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
David Harris
5dc4fb757a Continued busdp/ebu simplification 2022-08-25 10:20:02 -07:00
David Harris
24ce72f0a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
David Harris
89860588b8 Renamed AHB signals coming out of LSU to LSH_<AHBNAME> 2022-08-25 09:52:08 -07:00
Ross Thompson
bd9401179d BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
5cc4f1f1cd Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
1e1646da90 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
72b886ec8f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
Ross Thompson
bc0edc7bdf Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
David Harris
4ecdbb308a Renamed DCache to Cache in busdp/busfsm signal interface 2022-08-25 06:21:22 -07:00
David Harris
b9dc8d9e33 Cleanup typos 2022-08-25 04:32:19 -07:00
David Harris
cb2c0fe027 Minor name cleanups 2022-08-25 04:28:25 -07:00
David Harris
a3828420c0 Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
David Harris
fe3147806d removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
b3a13a01f8 Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
David Harris
e6077f1f16 Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00
David Harris
1ef0c7c2be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-24 16:30:28 -07:00
David Harris
9d5468887e Ram cleanup 2022-08-24 16:30:25 -07:00
Ross Thompson
b650d7e05a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
c636387613 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
012559169b Fixed lint errors with bram wrapper. 2022-08-24 13:19:23 -05:00
Ross Thompson
c6927d2ace Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
e2138d8d0f bram synthesis test 2022-08-23 19:34:45 -07:00
Ross Thompson
0c52c7f69c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 18:52:15 -05:00
Ross Thompson
ee3d968da0 Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite. 2022-08-23 18:51:11 -05:00
David Harris
8d48ff4e63 Fixed FPU-IEU forwarding stall 2022-08-23 14:14:41 -07:00
David Harris
8b2e368805 Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
David Harris
113258a0d0 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
69be6d0873 Simplify IEU-FP datapath 2022-08-23 11:16:36 -07:00
David Harris
746842107b Improved illegal instruction checking in FPU 2022-08-23 11:08:02 -07:00
David Harris
27cca2e3fd Fixed LSU typos 2022-08-23 10:23:08 -07:00
David Harris
46f30d3dbe Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 10:14:59 -07:00
David Harris
13831aa3d3 typo in srtfsm 2022-08-23 10:14:54 -07:00
Katherine Parry
f9aa94f87b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-23 16:36:32 +00:00
Katherine Parry
72a54ef621 renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
Ross Thompson
7080fe7788 Reversed order of supported sized in adrdecs. 2022-08-23 11:14:53 -05:00
Ross Thompson
b0606a1699 Replaced FPU data replicaiton on WriteData bus with 0 extention. 2022-08-23 10:46:03 -05:00
Ross Thompson
b9fadc11c3 Replaced LSU data replication with 0 extention. 2022-08-23 10:43:47 -05:00
Ross Thompson
cd0da2e3b3 Updated the names of the *WriteDataM inside the LSU to more meaningful names. 
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
 2022-08-23 10:34:39 -05:00
David Harris
7c91ed38a3 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
a9a5285ba8 Named HTRANS states in busfsm 2022-08-22 13:56:46 -07:00
David Harris
24a05c35d9 Renamed signals for LSU - FPU interface 2022-08-22 13:47:56 -07:00
David Harris
13d863a810 renamed GrantData to LSUGrant 2022-08-22 13:47:19 -07:00
David Harris
34eece10b8 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
7151befd04 Removed FStore2 and simplified HPTW 2022-08-22 13:29:54 -07:00
David Harris
bf54c1c868 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:29:20 -07:00
David Harris
fffad8b314 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-22 13:28:54 -07:00
David Harris
2170203847 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
Katherine Parry
a1f0c6c598 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 17:16:25 +00:00
Katherine Parry
1accb92745 sqrt passes - lint warnings remain 2022-08-22 17:16:12 +00:00
David Harris
564281b8c1 Removed 2-cycle FPU-IEU latency stall 2022-08-22 16:14:15 +00:00
David Harris
1404d1c248 moved CSA to generic 2022-08-22 08:41:23 +00:00
David Harris
a8870b70b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 08:28:31 +00:00
David Harris
b91f33372e Commented out unused comparators 2022-08-22 08:28:28 +00:00
Ross Thompson
88d34d0f56 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-21 16:03:11 -05:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
92c3cdc27d Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
a049f456e8 Removed logic from Verilog wrapper. 2022-08-21 14:07:43 -05:00
Katherine Parry
617dc02d01 fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Ross Thompson
96d6218078 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
c3bd396bdb Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00
Katherine Parry
0f077012c3 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
8eeca3319c radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
8f1d8669b0 fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
b13cdf79b3 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
baeafc4fd2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-02 07:34:12 -07:00
David Harris
d3e39763b6 Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
Ross Thompson
acd920ae2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
David Harris
0482bf4fc0 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
0b95ca129c Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
Ross Thompson
b8356c7449 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
171cf7413b Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
5d9dab6149 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
David Harris
8b44037f58 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
6e78b46761 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00
David Harris
76021769a7 lza cleanup 2022-08-01 16:01:02 -07:00
David Harris
47d204f4a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 15:47:58 -07:00
David Harris
c8d4f3a542 lza cleanup 2022-08-01 15:47:03 -07:00
David Harris
c531df9c4e lza cleanup 2022-08-01 15:43:48 -07:00
David Harris
5468a90cf3 lza cleanup 2022-08-01 15:40:12 -07:00
David Harris
4953ccf273 lza cleanup 2022-08-01 15:37:09 -07:00
Katherine Parry
66eca28ccd regression passes fpu tests 2022-08-01 19:56:25 +00:00
Katherine Parry
9672f5451a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 19:55:50 +00:00
David Harris
31215277ee more lza cleanup 2022-08-01 12:34:00 -07:00
David Harris
48500c642c LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
87e6402af6 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
5012b96120 LZA refactoring 2022-08-01 11:36:21 -07:00
Katherine Parry
75f39e0c5b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 18:35:07 +00:00
David Harris
231f52c1fd fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
e3b970d3ff Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
01359dbc4b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
Katherine Parry
de03954946 re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
David Harris
d2de84a456 Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
Ross Thompson
f1bd2524b7 Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
334008630f Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686 Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
458bfbf6f6 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
70032bf8f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
5cd6c8069d signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
7d026e02f2 cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
706bc819e1 cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
bd336f18b3 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
5b71ceac5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
0bfc3fda1b Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Katherine Parry
ee7932c804 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
David Harris
07c946bb04 Reset MSR on read 2022-07-22 04:29:27 +00:00
slmnemo
bfa500234d Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
Katherine Parry
270216dd02 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
67c99d3d1a added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Katherine Parry
e8c9830b88 turn off 2 word store durring non-fp instructions 2022-07-20 21:57:23 +00:00
Ross Thompson
9868e685a4 Minor cleanup of cache. 2022-07-19 23:04:23 -05:00
Ross Thompson
6c8ac7851e Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction. 2022-07-19 22:42:25 -05:00
Katherine Parry
fb890d621d moved ctrl signal registers into fctrl, also a lot of code cleaning 2022-07-20 02:27:39 +00:00
cturek
db39a05abc small changes 2022-07-20 01:36:25 +00:00
Katherine Parry
afcddf7035 oprimized zeros and replaced complex ?: with always_comb 2022-07-19 23:44:37 +00:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Katherine Parry
4c2afbbc4f moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
a590728350 reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
David Harris
59eb11b73a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 23:11:12 +00:00
Katherine Parry
e599f82b29 moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
921debf930 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
ea7b32a50b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-18 17:31:29 +00:00
Katherine Parry
5bb1478859 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
David Harris
7c744f0053 Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
David Harris
6e1d4ec4ed restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
Katherine Parry
a4cd157f00 forgot some files 2022-07-15 21:42:45 +00:00
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
Katherine Parry
e5a8ac2a44 renamed a file to fit diagram 2022-07-13 23:44:54 +00:00
Katherine Parry
7e163e22a3 some code cleanup 2022-07-13 15:28:22 -07:00
Katherine Parry
77ea4e47cb removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
26e39dd325 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
5c0ecfa433 forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
c72e4d43d2 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
905b7ffc84 moved unsused division code again 2022-07-07 16:41:26 -07:00
Katherine Parry
2bbde827e6 Revert "moved old divsqrt to unusedsrc" 
This reverts commit c9f5ae12ea.
 2022-07-07 16:29:17 -07:00
Katherine Parry
c9f5ae12ea moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
08ae2db080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
cb33d2289b fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
9ef38145d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
a599084b88 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
846f12aa2e new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
01e6d69a67 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
d033659beb Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
e7fe7ad0c8 AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
4723ff559c Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
aa3dc8bfe1 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
4c48d71e4b removed delay in ahblite 2022-07-05 04:59:28 +00:00
Katherine Parry
010a05f583 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
bde1c5eb1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
52dbc9f8be FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
575b73fa8c some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
f2d05911ca very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
Katherine Parry
f25bb4a384 radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
2d5d1f4e8f radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
06f7f9b147 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
d16ae7c305 passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
913a381442 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
c1b4e7fd2c modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a65c0eb679 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
d058ec6329 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
fc75fc633f division by zero added 2022-06-24 01:09:44 +00:00
Katherine Parry
86cdbd90e6 forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
97ded2cdd9 div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
d17596353b lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
b54d84195f added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
ded2631567 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
David Harris
2c4b86c703 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
ceddc99ac9 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
Katherine Parry
49067792dc fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
Madeleine Masser-Frye
0161683945 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
fe31ee92e8 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Katherine Parry
93906b9457 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
e121dcd4af postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
c2493168b6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
76e30ed8ab cleanup, plots for paper 2022-06-15 18:28:36 +00:00
Katherine Parry
11b252a735 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
Katherine Parry
998876ce49 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
566001e07b fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00