Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
bd07a60c07
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
11a057b0b3
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
2ed0b239e8
Added preload pointing to data.mem in ram1p1rwbe.sv
2024-08-02 15:21:15 -05:00
Jacob Pease
1e20d5aea6
Added preload pointing to data.mem in ram1p1rwbe.sv
2024-08-02 15:21:15 -05:00
Rose Thompson
6496454054
Merge pull request #895 from davidharrishmc/dev
...
Fix Issue 894 about floating-point decoding of reserved rm/frm
2024-07-25 11:51:32 -05:00
Rose Thompson
2e4ca4c876
Merge pull request #895 from davidharrishmc/dev
...
Fix Issue 894 about floating-point decoding of reserved rm/frm
2024-07-25 11:51:32 -05:00
David Harris
faa1378920
Legalized PMPconfig WARL
2024-07-25 09:43:54 -07:00
David Harris
7360be1234
Legalized PMPconfig WARL
2024-07-25 09:43:54 -07:00
David Harris
d5af25ffbf
CHeck legal rnum field when decoding aes64ks1i
2024-07-25 09:19:23 -07:00
David Harris
c637e40058
CHeck legal rnum field when decoding aes64ks1i
2024-07-25 09:19:23 -07:00
Jacob Pease
6fc10adc25
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Jacob Pease
336a413f31
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
David Harris
5bf7250687
Issue #894 : trap on floating-point ops with reserved rounding modes: detect Zfa flt
2024-07-25 09:09:13 -07:00
David Harris
7234abebef
Issue #894 : trap on floating-point ops with reserved rounding modes: detect Zfa flt
2024-07-25 09:09:13 -07:00
David Harris
f7dd49cc6c
Issue #894 : trap on floating-point ops with reserved rounding modes
2024-07-25 06:59:58 -07:00
David Harris
337e40ac1b
Issue #894 : trap on floating-point ops with reserved rounding modes
2024-07-25 06:59:58 -07:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
c11036358a
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
9404a339ee
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
Rose Thompson
7960f26e84
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
Rose Thompson
6c212ebf0e
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
35efbd6a54
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Jacob Pease
c18b3d814d
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Jacob Pease
f1cc7dd5a3
Fixed verilog bugs.
2024-07-23 17:26:39 -05:00
Rose Thompson
e8e71ad643
Code cleanup.
2024-07-23 16:35:05 -05:00
Rose Thompson
bfb3b63a24
Code cleanup.
2024-07-23 16:35:05 -05:00
Rose Thompson
57ea39d685
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
fe9ac36928
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
54e0289608
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Rose Thompson
da2511c63c
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Rose Thompson
1eff86b7ae
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
7bc04702a7
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
f20b82b14e
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
825dbefcb2
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
d706b5b898
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
b30656447f
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
94a1ce32e7
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
c6c2240630
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
121342f4cc
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Rose Thompson
3c06556833
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Jacob Pease
c50df29e58
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-22 13:06:05 -05:00
Jacob Pease
6a9141e3be
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-22 13:06:05 -05:00
Jacob Pease
a722c3c0a1
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Rose Thompson
00c30239bf
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
35e69944fa
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
02f108345a
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
David Harris
c4400dfeb0
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
David Harris
13f1aa1ebf
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
David Harris
c64c12dc6c
Detect illegal compressed immediates, hints
2024-07-18 22:48:32 -07:00
David Harris
12c8449275
Detect illegal compressed immediates, hints
2024-07-18 22:48:32 -07:00
David Harris
945722cd5b
Neatly formatted decompress.sv
2024-07-18 22:01:43 -07:00
David Harris
bd1658754f
Neatly formatted decompress.sv
2024-07-18 22:01:43 -07:00
David Harris
ebea314a6e
Modified decompressor to look for illegal x0 values and hints
2024-07-18 21:38:17 -07:00
David Harris
a4e84d6f15
Modified decompressor to look for illegal x0 values and hints
2024-07-18 21:38:17 -07:00
David Harris
3b4726ea99
Check legal compressed nonzero destination registers, add c.nop decoding
2024-07-18 09:30:16 -07:00
David Harris
1637f4f1e3
Check legal compressed nonzero destination registers, add c.nop decoding
2024-07-18 09:30:16 -07:00
David Harris
df063acf61
Refactored decompression to use simpler default illegal instruction
2024-07-18 08:26:58 -07:00
David Harris
566583639d
Refactored decompression to use simpler default illegal instruction
2024-07-18 08:26:58 -07:00
David Harris
25f271064f
Fixed slli.uw bug reported by Lee Moore 16 July 2024
2024-07-16 09:28:05 -07:00
David Harris
8f83ff1a94
Fixed slli.uw bug reported by Lee Moore 16 July 2024
2024-07-16 09:28:05 -07:00
Ross Thompson
f0096f5a43
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11
Yay! the trigger is correctly working now!
2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8
Really close to having the trigger in module work.
...
Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
David Harris
84c687080d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb
...
Reduce Bit widths for IDIV on FPU
2024-07-05 21:42:19 -07:00
David Harris
ffb248dc65
Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit
2024-07-05 21:32:57 -07:00
David Harris
af4403342f
renamed run_vcs.py to run_vcs, added instr/data in ebu
2024-07-03 08:02:38 -07:00
Kevin Kim
b04d387e7c
removed redundant signals
2024-06-28 22:13:35 -07:00
Kevin Kim
6cb6ff429b
Revert "intdivble changes"
...
This reverts commit 3618c6c593
2024-06-28 21:28:09 -07:00
Kevin Kim
3618c6c593
intdivble changes
2024-06-28 21:19:10 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs
2024-06-26 22:15:18 -07:00
Jordan Carlin
c3cb4e5d1c
Fix FPU without S_SUPPORTED - #840
2024-06-26 22:00:29 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Kevin Kim
eeea783da0
lint
2024-06-21 23:15:34 -07:00
Kevin Kim
e6dc50308a
integer postprocessing hardware matches diagram
2024-06-21 21:50:55 -07:00
Kevin Kim
00bf3faa9c
changed intdivb width
2024-06-21 21:31:19 -07:00
Kevin Kim
9a59c8e07f
reduced bit widths for integer on fpu
2024-06-20 23:46:45 -07:00
Ross Thompson
249d58244a
It's working!!!!!!
2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
David Harris
0ab3f28991
Lint cleanup
2024-06-20 00:10:03 -07:00
David Harris
5f1ee1ac85
Fixed undriven signal in certain config
2024-06-19 15:12:35 -07:00
David Harris
9922b24cbe
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-06-19 14:13:08 -07:00
Ross Thompson
685f4d3807
Removed the last of the ***.
2024-06-19 14:00:31 -07:00
Ross Thompson
7f0ba87231
Updated comments in uart.
2024-06-19 13:51:30 -07:00
Ross Thompson
91c844ca45
Removed more *** from camline and csrc.
2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59
Moved the *** from trap to an issue.
2024-06-19 12:31:24 -07:00
Ross Thompson
9b6b6617af
Cleaned up hptw.
2024-06-19 12:02:56 -07:00
Ross Thompson
24916d42e2
Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw.
2024-06-19 11:40:02 -07:00
Ross Thompson
71f267a17a
Added InstrUpdateDAF to the HPTW.
2024-06-19 11:09:49 -07:00
Ross Thompson
77523c52c2
LSU no longer has ***.
2024-06-19 10:56:07 -07:00
Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
Ross Thompson
4911642427
Removed *** and updated comments for bpred and align.
2024-06-19 10:31:44 -07:00
Ross Thompson
f0e5bbef0c
Removed remaining *** from IFU.
2024-06-19 09:52:40 -07:00
Ross Thompson
cc58bfdcf3
Removed more *** from the ifu.
2024-06-19 09:49:17 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Ross Thompson
ab1af0fabf
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2024-06-19 09:25:39 -07:00
David Harris
10e6d5846b
Removed unnecessary Umfirst from early termination
2024-06-19 09:18:51 -07:00
David Harris
4b4980e42d
Fixed undriven OutFmt
2024-06-19 09:17:32 -07:00
David Harris
54cb612577
Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU
2024-06-19 07:48:54 -07:00
Ross Thompson
2581ea0b74
Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.
2024-06-18 16:48:49 -07:00
David Harris
301ded05f8
Unused signal cleanup
2024-06-18 08:15:48 -07:00
David Harris
cb563e8018
Clean up unused signals
2024-06-18 08:07:14 -07:00
Ross Thompson
00e0549c36
I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word.
...
The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.
2024-06-18 07:44:19 -07:00
David Harris
c1fd7a9589
Removed unused signals
2024-06-18 07:28:52 -07:00
David Harris
8bae52b09d
Lint cleanup of unused signals
2024-06-18 06:49:17 -07:00
David Harris
45f505250c
Lint cleanup
2024-06-18 06:23:43 -07:00
David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
cac67aae4f
Lint cleanup
2024-06-18 05:58:54 -07:00
David Harris
ecae1100f6
Lint cleanup
2024-06-18 05:49:49 -07:00
David Harris
7509e856df
Removed asynchronous reset causing lint issue in peripherals
2024-06-18 05:49:12 -07:00
David Harris
2fc9edff45
Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly
2024-06-18 04:40:38 -07:00
Ross Thompson
cccb40e4b5
Got the tracer not overrunning ethernet buffers so frames are not being dropped.
2024-06-17 09:16:24 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
6789f32154
Starting code cleanup
2024-06-14 02:54:43 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Rose Thompson
b77fcd70e6
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-13 13:58:07 -05:00
David Harris
28142eff64
Formatting shiftcorrection
2024-06-12 04:25:13 -07:00
David Harris
b7e2f34966
shiftcorrection cleanup
2024-06-12 03:59:55 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
David Harris
e02c1008bc
postprocessor shift amount simplification
2024-06-10 07:55:35 -07:00
David Harris
3284dd2112
Removed unnecessary Zero checking on FmaPreResultSubnorm
2024-06-10 07:45:03 -07:00
David Harris
4c066c078f
Removing two unnecessary 0's from fmashiftcalc interface
2024-06-10 07:38:03 -07:00
David Harris
1873064be5
Simplified fround exact case
2024-06-10 06:23:42 -07:00
David Harris
5094122048
Simplifying fround
2024-06-10 06:11:55 -07:00
David Harris
8b887755c9
Simplified 3:1 mux to 2:1 mux when only Zbkc is supported and clmulr is not needed
2024-06-10 02:34:35 -07:00
Rose Thompson
5dfde808f0
Merge pull request #827 from davidharrishmc/dev
...
Fixed support for individual crypto extensions without Zb*
2024-06-06 09:31:07 -05:00
David Harris
9489771bd7
Fixed support for individual crypto extensions without Zb*
2024-06-05 22:57:39 -07:00
Rose Thompson
fc62f80407
Closer to fully working hardware tracer.
2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223
now have a working ethernet daemon to collect frames and partially decode into RVVI.
2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb
The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
2024-06-03 18:10:25 -05:00
Rose Thompson
0ca10e7ee2
Last of the branch predictor signal name updates.
2024-06-02 17:01:51 -05:00
Rose Thompson
04744032d8
Updated more signal names to match book.
2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6
Signal name changes to match book.
2024-06-02 16:32:25 -05:00
Rose Thompson
731e1fe08f
Updated spill logic to reflect changes in textbook.
2024-06-02 15:48:42 -05:00
Rose Thompson
a830bd57f0
Have to reverse the byte order for ethernet frame length.
2024-05-31 17:46:43 -05:00
Rose Thompson
e05ebc30b8
Almost worked out the bugs in packetizer.
2024-05-31 16:48:41 -05:00
Rose Thompson
0dccc6051d
draft of receiving code to unpack the ethernet frames into rvvi.
2024-05-31 13:55:25 -05:00
Rose Thompson
1df3e5239a
This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer.
...
wireshark is able to capture the frames and they match the expected data!
2024-05-30 17:57:28 -05:00
Rose Thompson
ca90c6ba48
Added the ethernet files. These are part of another repo.
...
We should remove before mainlining this.
2024-05-30 16:33:49 -05:00
