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Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.

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This commit is contained in:
Rose Thompson 2024-07-24 12:47:50 -05:00
parent 27f89fcdbd
commit b1a711ae0f
14 changed files with 24 additions and 56 deletions
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4
bin/wsim
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@ -33,6 +33,7 @@ parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_
parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
args = parser.parse_args()
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
ElfFile=""
@ -64,6 +65,9 @@ if (args.gui or args.ccov or args.fcov or args.lockstep):
if (args.vcd):
args.args += " -DMAKEVCD=1"
if (args.rvvi):
args.args += " -GRVVI_SYNTH_SUPPORTED=1"
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0

4
config/derivlist.txt
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@ -57,10 +57,6 @@ EXT_MEM_RANGE 64'h0FFFFFFF
SDC_SUPPORTED 1
PLIC_SDC_ID 32'd20
BPRED_SIZE 32'd12
RVVI_SYNTH_SUPPORTED 1
RVVI_INIT_TIME_OUT 32'd100000000
RVVI_PACKET_DELAY 32'd400
# The syn configurations are trimmed down for faster synthesis.
deriv syn_rv32e rv32e

5
config/rv32e/config.vh
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@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;
// debug tools
localparam logic RVVI_SYNTH_SUPPORTED = 0;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
`include "config-shared.vh"

5
config/rv32gc/config.vh
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@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd2;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;
// debug tools
localparam logic RVVI_SYNTH_SUPPORTED = 0;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
`include "config-shared.vh"

5
config/rv32i/config.vh
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@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;
// debug tools
localparam logic RVVI_SYNTH_SUPPORTED = 0;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
`include "config-shared.vh"

5
config/rv32imc/config.vh
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@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;
// debug tools
localparam logic RVVI_SYNTH_SUPPORTED = 0;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
`include "config-shared.vh"

5
config/rv64gc/config.vh
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@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;
// debug tools
localparam logic RVVI_SYNTH_SUPPORTED = 0;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
`include "config-shared.vh"

5
config/rv64i/config.vh
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@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4;
// Memory synthesis configuration
localparam logic USE_SRAM = 0;
// debug tools
localparam logic RVVI_SYNTH_SUPPORTED = 0;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
`include "config-shared.vh"

5
config/shared/parameter-defs.vh
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@ -200,9 +200,6 @@ localparam cvw_t P = '{
DURLEN : DURLEN,
DIVb : DIVb,
DIVBLEN : DIVBLEN,
INTDIVb : INTDIVb,
RVVI_SYNTH_SUPPORTED : RVVI_SYNTH_SUPPORTED,
RVVI_INIT_TIME_OUT : RVVI_INIT_TIME_OUT,
RVVI_PACKET_DELAY : RVVI_PACKET_DELAY
INTDIVb : INTDIVb
};

4
fpga/generator/wally.tcl
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@ -89,8 +89,8 @@ report_clock_interaction -file re
write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc
#source ../constraints/small-debug.xdc
source ../constraints/small-debug-rvvi.xdc
} else {
# source ../constraints/vcu-small-debug.xdc

8
fpga/src/fpgaTopArtyA7.sv
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@ -28,7 +28,7 @@
import cvw::*;
module fpgaTop
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
input south_reset,
@ -1117,9 +1117,11 @@ module fpgaTop
(* mark_debug = "true" *) logic IlaTrigger;
if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
localparam MAX_CSRS = 3;
localparam TOTAL_CSRS = 36;
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd100000000;
localparam [31:0] RVVI_PACKET_DELAY = 32'd400;
// pipeline controlls
logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
@ -1218,7 +1220,7 @@ module fpgaTop
logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
eth_mac_mii_fifo #(.TARGET("XILINX"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset),

4
src/cvw.sv
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@ -296,10 +296,6 @@ typedef struct packed {
int DIVBLEN ;
// integer division/remainder constants
int INTDIVb ;
// debug tools
logic RVVI_SYNTH_SUPPORTED;
logic [31:0] RVVI_INIT_TIME_OUT;
logic [31:0] RVVI_PACKET_DELAY;
} cvw_t;
endpackage

9
src/rvvi/packetizer.sv
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@ -28,7 +28,10 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module packetizer import cvw::*; #(parameter cvw_t P,
parameter integer MAX_CSRS)(
parameter integer MAX_CSRS,
parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4,
parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2
)(
input logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi,
input logic valid,
input logic m_axi_aclk, m_axi_aresetn,
@ -100,8 +103,8 @@ module packetizer import cvw::*; #(parameter cvw_t P,
// have to count at least 250 ms after reset pulled to wait for the phy to actually be ready
// at 20MHz 250 ms is 250e-3 / (1/20e6) = 5,000,000.
counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount);
assign CountFlag = RstCount == P.RVVI_INIT_TIME_OUT;
assign DelayFlag = RstCount == P.RVVI_PACKET_DELAY;
assign CountFlag = RstCount == RVVI_INIT_TIME_OUT;
assign DelayFlag = RstCount == RVVI_PACKET_DELAY;
counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount);

12
testbench/testbench.sv
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@ -33,9 +33,6 @@
`include "idv/idv.svh"
`endif
// *** bug replace with config?
`define RVVI_SYNTH_SUPPORTED 1
import cvw::*;
module testbench;
@ -46,6 +43,7 @@ module testbench;
parameter BPRED_LOGGER=0;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
parameter RVVI_SYNTH_SUPPORTED=0;
`ifdef USE_IMPERAS_DV
import idvPkg::*;
@ -603,9 +601,11 @@ module testbench;
clk = 1'b1; # 5; clk = 1'b0; # 5;
end
if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
localparam MAX_CSRS = 5;
logic valid;
localparam logic [31:0] RVVI_INIT_TIME_OUT = 32'd4;
localparam logic [31:0] RVVI_PACKET_DELAY = 32'd2;
logic valid;
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
localparam TOTAL_CSRS = 36;
@ -702,7 +702,7 @@ module testbench;
logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset),