Changes are confirmed to work on the FPGA.

src/rvvi/rvvisynth.sv

@@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module rvvisynth import cvw::*; #(parameter cvw_t P,
-                                  parameter integer MAX_CSRS = 3, 
+                                  parameter integer MAX_CSRS = 5, 
                                   parameter integer TOTAL_CSRS = 36)(
   input logic clk, reset,
   input logic                                     StallE, StallM, StallW, FlushE, FlushM, FlushW,

testbench/testbench.sv

@@ -604,7 +604,7 @@ module testbench;
   end
 
   if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
-    localparam MAX_CSRS = 3;
+    localparam MAX_CSRS = 5;
     logic                       valid;
     logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;