Updated wally source files for zsbl testing.

config/derivlist.txt

@@ -50,7 +50,8 @@ PLIC_NUM_SRC        32'd53
 deriv fpga  buildroot 
 BOOTROM_PRELOAD     1
 UNCORE_RAM_BASE     64'h2000
-UNCORE_RAM_RANGE    64'hFFF
+UNCORE_RAM_RANGE    64'h1FFF
+BOOTROM_RANGE       64'hFFF
 EXT_MEM_SUPPORTED   1
 EXT_MEM_BASE        64'h80000000
 EXT_MEM_RANGE       64'h0FFFFFFF

fpga/constraints/constraints-ArtyA7.xdc

@@ -97,16 +97,21 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
 #set_property PULLUP true [get_ports {SDCCmd}]
 #set_property PULLUP true [get_ports {SDCCD}]
 
-set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[3]}]
-set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
-set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
-set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[0]}]
+# SDCDat[3]
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}]
+# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
+# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
+# SDCDat[0]
+set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}]
 set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}]
 set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}]
 set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}]
 
-set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
-set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
+set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCCS}]
+
+set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
+set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCIn}]
 
 set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
 set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]

src/uncore/spi_apb.sv

@@ -148,6 +148,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     // APB access
     assign Entry = {PADDR[7:2],2'b00};  //  32-bit word-aligned accesses
     assign Memwrite = PWRITE & PENABLE & PSEL;  // Only write in access phase
+    // JACOB: This shouldn't behave this way
     assign PREADY = TransmitInactive; // Tie PREADY to transmission for hardware interlock
 
     // Account for subword read/write circuitry
@@ -366,22 +367,25 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode));
     assign Active0 = (state == ACTIVE_0);
 
-    // Signal tracks which edge of sck to shift data
+  // Signal tracks which edge of sck to shift data
+  // Jacob: We need to confirm that this represents the actual polarity and phase options for sampling.
+  //        The first option now samples on the leading edge and shifts on the falling edge like it's supposed to.
+  //        We need to confirm the validity of the other options. 
     always_comb
         case(SckMode[1:0])
-            2'b00: ShiftEdge = ~SPICLK & SCLKenable;
-            2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable);
-            2'b10: ShiftEdge = SPICLK & SCLKenable;
-            2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable);
+            2'b00: ShiftEdge = SPICLK & SCLKenable;
+            2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); // Probably wrong
+            2'b10: ShiftEdge = ~SPICLK & SCLKenable; // Probably wrong
+            2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); // Probably wrong
             default: ShiftEdge = SPICLK & SCLKenable;
         endcase
 
     // Transmit shift register
     assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
     always_ff @(posedge PCLK)
-        if(~PRESETn)                        TransmitShiftReg <= 8'b0; 
+        if(~PRESETn)                        TransmitShiftReg <= 8'b0; // Temporarily changing to 1s 
         else if (TransmitShiftRegLoad)      TransmitShiftReg <= TransmitDataEndian;
-        else if (ShiftEdge & Active)        TransmitShiftReg <= {TransmitShiftReg[6:0], 1'b0};
+        else if (ShiftEdge & Active)        TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]}; // Temporarily changing to 1s
     
     assign SPIOut = TransmitShiftReg[7];
 

src/uncore/uncore.sv

@@ -172,7 +172,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
       .PREADY(PREADY[5]), .PRDATA(PRDATA[5]),
       .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(SDCIntr));                                      
   end else begin : sdc
-    assign SDCCmd = '0; assign SDCCS = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0;
+    assign SDCCmd = '0; assign SDCCS = 4'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0;
   end
   
 

src/wally/wallypipelinedsoc.sv

@@ -90,7 +90,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
       .UARTSout, .MTIME_CLINT, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK);
   end else begin
     assign {HRDATA, HREADY, HRESP, HSELEXT, MTimerInt, MSwInt, MExtInt, SExtInt,
-            MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; 
+            MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS, SPICLK, SDCCmd, SDCCS, SDCCLK} = '0; 
   end
 
 endmodule

testbench/wallywrapper.sv

@@ -32,7 +32,7 @@ module wallywrapper import cvw::*;(
   input logic clk,
   input logic reset_ext,
   input logic SPIIn,
-  input logic SDCIntr
+  input logic SDCIn
 );
  
 `include "parameter-defs.vh"
@@ -56,10 +56,14 @@ module wallywrapper import cvw::*;(
   logic        UARTSin, UARTSout;
   logic        SPIOut;
   logic [3:0]  SPICS;
+  logic        SPICLK;
+
+  logic        SDCCmd;
+  logic [3:0]  SDCCS;
+  logic        SDCCLK;
 
   logic        HREADY;
   logic        HSELEXT;
-  logic        HSELEXTSDC;
   
   
   // instantiate device to be tested
@@ -71,9 +75,9 @@ module wallywrapper import cvw::*;(
     assign HRDATAEXT = 0;
 
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
-                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr); 
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); 
 
 endmodule