Rose Thompson 54e0289608 Fixed bugs in the rvvi synth logic which encoded csr instructions.		2024-07-23 16:16:11 -05:00
..
cache	Clean up unused signals	2024-06-18 08:07:14 -07:00
ebu	renamed run_vcs.py to run_vcs, added instr/data in ebu	2024-07-03 08:02:38 -07:00
fpu	Revert "intdivble changes"	2024-06-28 21:28:09 -07:00
generic	Removed *** from IFU, lrcs.	2024-06-19 09:40:35 -07:00
hazard	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
ieu	Fixed slli.uw bug reported by Lee Moore 16 July 2024	2024-07-16 09:28:05 -07:00
ifu	Detect illegal compressed immediates, hints	2024-07-18 22:48:32 -07:00
lsu	Lint cleanup	2024-06-20 00:10:03 -07:00
mdu	Unused signal cleanup	2024-06-18 08:15:48 -07:00
mmu	Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit	2024-07-05 21:32:57 -07:00
privileged	Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode	2024-07-22 08:45:08 -07:00
rvvi	Fixed bugs in the rvvi synth logic which encoded csr instructions.	2024-07-23 16:16:11 -05:00
uncore	Updated comments in uart.	2024-06-19 13:51:30 -07:00
wally	Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.	2024-07-23 13:18:03 -05:00
cvw.sv	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00