Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
Ross Thompson
4911642427
Removed *** and updated comments for bpred and align.
2024-06-19 10:31:44 -07:00
Ross Thompson
f0e5bbef0c
Removed remaining *** from IFU.
2024-06-19 09:52:40 -07:00
Ross Thompson
cc58bfdcf3
Removed more *** from the ifu.
2024-06-19 09:49:17 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Ross Thompson
ab1af0fabf
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2024-06-19 09:25:39 -07:00
David Harris
10e6d5846b
Removed unnecessary Umfirst from early termination
2024-06-19 09:18:51 -07:00
David Harris
4b4980e42d
Fixed undriven OutFmt
2024-06-19 09:17:32 -07:00
David Harris
54cb612577
Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU
2024-06-19 07:48:54 -07:00
Ross Thompson
2581ea0b74
Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.
2024-06-18 16:48:49 -07:00
David Harris
301ded05f8
Unused signal cleanup
2024-06-18 08:15:48 -07:00
David Harris
cb563e8018
Clean up unused signals
2024-06-18 08:07:14 -07:00
Ross Thompson
00e0549c36
I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word.
...
The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.
2024-06-18 07:44:19 -07:00
David Harris
c1fd7a9589
Removed unused signals
2024-06-18 07:28:52 -07:00
David Harris
8bae52b09d
Lint cleanup of unused signals
2024-06-18 06:49:17 -07:00
David Harris
45f505250c
Lint cleanup
2024-06-18 06:23:43 -07:00
David Harris
3fa37b0233
Lint cleanup
2024-06-18 06:15:17 -07:00
David Harris
cac67aae4f
Lint cleanup
2024-06-18 05:58:54 -07:00
David Harris
ecae1100f6
Lint cleanup
2024-06-18 05:49:49 -07:00
David Harris
7509e856df
Removed asynchronous reset causing lint issue in peripherals
2024-06-18 05:49:12 -07:00
David Harris
2fc9edff45
Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly
2024-06-18 04:40:38 -07:00
Ross Thompson
cccb40e4b5
Got the tracer not overrunning ethernet buffers so frames are not being dropped.
2024-06-17 09:16:24 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c
Simplified outdated documentation pointers
2024-06-14 03:42:15 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
6789f32154
Starting code cleanup
2024-06-14 02:54:43 -07:00
Ross Thompson
47523c97ac
Getting closer to figuring out the lost ethernet frame bugs.
2024-06-13 15:46:54 -07:00
Rose Thompson
b77fcd70e6
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-13 13:58:07 -05:00
David Harris
28142eff64
Formatting shiftcorrection
2024-06-12 04:25:13 -07:00
David Harris
b7e2f34966
shiftcorrection cleanup
2024-06-12 03:59:55 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
David Harris
e02c1008bc
postprocessor shift amount simplification
2024-06-10 07:55:35 -07:00
David Harris
3284dd2112
Removed unnecessary Zero checking on FmaPreResultSubnorm
2024-06-10 07:45:03 -07:00
David Harris
4c066c078f
Removing two unnecessary 0's from fmashiftcalc interface
2024-06-10 07:38:03 -07:00
David Harris
1873064be5
Simplified fround exact case
2024-06-10 06:23:42 -07:00
David Harris
5094122048
Simplifying fround
2024-06-10 06:11:55 -07:00
David Harris
8b887755c9
Simplified 3:1 mux to 2:1 mux when only Zbkc is supported and clmulr is not needed
2024-06-10 02:34:35 -07:00
Rose Thompson
5dfde808f0
Merge pull request #827 from davidharrishmc/dev
...
Fixed support for individual crypto extensions without Zb*
2024-06-06 09:31:07 -05:00
David Harris
9489771bd7
Fixed support for individual crypto extensions without Zb*
2024-06-05 22:57:39 -07:00
Rose Thompson
fc62f80407
Closer to fully working hardware tracer.
2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223
now have a working ethernet daemon to collect frames and partially decode into RVVI.
2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb
The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
2024-06-03 18:10:25 -05:00
Rose Thompson
0ca10e7ee2
Last of the branch predictor signal name updates.
2024-06-02 17:01:51 -05:00
Rose Thompson
04744032d8
Updated more signal names to match book.
2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6
Signal name changes to match book.
2024-06-02 16:32:25 -05:00
Rose Thompson
731e1fe08f
Updated spill logic to reflect changes in textbook.
2024-06-02 15:48:42 -05:00
Rose Thompson
a830bd57f0
Have to reverse the byte order for ethernet frame length.
2024-05-31 17:46:43 -05:00
Rose Thompson
e05ebc30b8
Almost worked out the bugs in packetizer.
2024-05-31 16:48:41 -05:00
Rose Thompson
0dccc6051d
draft of receiving code to unpack the ethernet frames into rvvi.
2024-05-31 13:55:25 -05:00
Rose Thompson
1df3e5239a
This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer.
...
wireshark is able to capture the frames and they match the expected data!
2024-05-30 17:57:28 -05:00
Rose Thompson
ca90c6ba48
Added the ethernet files. These are part of another repo.
...
We should remove before mainlining this.
2024-05-30 16:33:49 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
84946919a4
Changed name CacheWriteData to WriteData.
2024-05-28 18:00:39 -05:00
Rose Thompson
273b41df99
Changed name of cache parameter NUMLINES to NUMSETS to better match book.
2024-05-28 17:55:43 -05:00
Jordan Carlin
6f7a802b86
Merge branch 'main' of https://github.com/openhwgroup/cvw into fround_fixes
2024-05-26 14:40:26 -07:00
Jordan Carlin
b830d20f2d
Modify Fround Tmask to work for X=1
2024-05-25 12:56:02 -07:00
Jordan Carlin
fb77440a64
Update fpctrl fmt to work for fround instructions
2024-05-24 15:33:45 -07:00
Jordan Carlin
ae29a9b861
Update control bits for froundnx
2024-05-24 15:19:20 -07:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
David Harris
a95977590d
AES cleanup
2024-05-24 14:28:30 -07:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
David Harris
b2689b4f01
AES cleanup
2024-05-24 14:13:57 -07:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
...
Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
David Harris
ec5c67a5c1
AES cleanup
2024-05-24 13:48:53 -07:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
David Harris
e626052ec9
simplified AES32de mixcolumns because input is only one byte
2024-05-23 22:30:25 -07:00
David Harris
b0d1344121
Commented sha instructions
2024-05-23 22:06:37 -07:00
David Harris
ac153bc4ed
More simplifying sha512_32
2024-05-23 05:46:56 -07:00
David Harris
d9a1691c83
Simplified sha512_32
2024-05-23 05:39:50 -07:00
David Harris
c160ced2d2
Zk* cleanup
2024-05-22 15:01:20 -07:00
David Harris
3ad815ce34
Reordered Zicond support in ALU
2024-05-22 08:29:08 -07:00
Rose Thompson
e5b8fd35b0
Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.
2024-05-22 09:56:12 -05:00
David Harris
a17204b0fe
Continued bmu cleanup
2024-05-22 00:48:04 -07:00
David Harris
88eb7bd045
Pulled brev8 out of byteop so redundant byteop logic is not needed in zbkb
2024-05-22 00:22:53 -07:00
Rose Thompson
b116c0c902
Lots of progress on the rvvisynth to ethernet packetizer.
...
Almost producing axi4 commands.
2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee
Removed prefix from rvvi hierarchy so it works without testbench.
2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322
Fixed some references to rvvi.
2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf
Closer to synthesized rvvi
2024-05-21 12:42:43 -05:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
3df5a5abdd
Remove additional bitwise operator
2024-05-15 09:29:54 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
...
Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
175c18da01
Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes
2024-05-13 15:16:00 -07:00
David Harris
2dfada0687
Started parameterizing FMA
2024-05-13 14:01:36 -07:00
David Harris
c2b9e326ca
Fround cleanup
2024-05-13 13:27:29 -07:00
David Harris
e87a269f59
Fix fcvt.lu.s bug and lint issue in packoutput
2024-05-12 11:31:27 -07:00
David Harris
380d88fc68
Merged config-shared after fma fix
2024-05-12 11:10:55 -07:00
David Harris
009d251433
Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases
2024-05-11 22:32:51 -07:00
Katherine Parry
807ef44772
fixed fma testfloat issue #578
2024-05-10 18:12:11 -07:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
10b08f8039
Updated brach predictor names to more logical names and match textbook.
2024-05-10 08:51:12 -05:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
David Harris
fcd75fd6b6
Fixed shiftcorrection typo causing failure on testfloat fcvt tests
2024-05-07 14:27:44 -07:00
David Harris
bdc2ad494f
Shared AND gate in ALU for extract / and paths
2024-05-03 09:07:33 -07:00
