Rose Thompson
57ea39d685
Fixed rvvi csr counting.
2024-07-23 16:22:23 -05:00
Rose Thompson
54e0289608
Fixed bugs in the rvvi synth logic which encoded csr instructions.
2024-07-23 16:16:11 -05:00
Rose Thompson
1eff86b7ae
Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
2024-07-23 13:18:03 -05:00
Rose Thompson
c463201d68
Moved all rvvi files to rvvi directory.
2024-07-23 13:03:21 -05:00
Rose Thompson
825dbefcb2
Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b
Resolved more lint errors in the rvvi synthesized hardware.
2024-07-23 12:23:04 -05:00
Rose Thompson
94a1ce32e7
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
121342f4cc
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Rose Thompson
00c30239bf
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
David Harris
c4400dfeb0
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
...
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
David Harris
c64c12dc6c
Detect illegal compressed immediates, hints
2024-07-18 22:48:32 -07:00
David Harris
945722cd5b
Neatly formatted decompress.sv
2024-07-18 22:01:43 -07:00
David Harris
ebea314a6e
Modified decompressor to look for illegal x0 values and hints
2024-07-18 21:38:17 -07:00
David Harris
3b4726ea99
Check legal compressed nonzero destination registers, add c.nop decoding
2024-07-18 09:30:16 -07:00
David Harris
df063acf61
Refactored decompression to use simpler default illegal instruction
2024-07-18 08:26:58 -07:00
David Harris
25f271064f
Fixed slli.uw bug reported by Lee Moore 16 July 2024
2024-07-16 09:28:05 -07:00
Ross Thompson
f0096f5a43
Yay. It's actually working! The FPGA/ImperasDV hybrid is working.
2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11
Yay! the trigger is correctly working now!
2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8
Really close to having the trigger in module work.
...
Can trigger on the data of the correct frame, but trigger in is still not
working.
2024-07-09 19:04:51 -05:00
David Harris
84c687080d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb
...
Reduce Bit widths for IDIV on FPU
2024-07-05 21:42:19 -07:00
David Harris
ffb248dc65
Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit
2024-07-05 21:32:57 -07:00
David Harris
af4403342f
renamed run_vcs.py to run_vcs, added instr/data in ebu
2024-07-03 08:02:38 -07:00
Kevin Kim
b04d387e7c
removed redundant signals
2024-06-28 22:13:35 -07:00
Kevin Kim
6cb6ff429b
Revert "intdivble changes"
...
This reverts commit 3618c6c593
2024-06-28 21:28:09 -07:00
Kevin Kim
3618c6c593
intdivble changes
2024-06-28 21:19:10 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs
2024-06-26 22:15:18 -07:00
Jordan Carlin
c3cb4e5d1c
Fix FPU without S_SUPPORTED - #840
2024-06-26 22:00:29 -07:00
Ross Thompson
612a281f62
Added module to receive ethernet frame and trigger the ila.
2024-06-26 11:05:31 -07:00
Kevin Kim
eeea783da0
lint
2024-06-21 23:15:34 -07:00
Kevin Kim
e6dc50308a
integer postprocessing hardware matches diagram
2024-06-21 21:50:55 -07:00
Kevin Kim
00bf3faa9c
changed intdivb width
2024-06-21 21:31:19 -07:00
Kevin Kim
9a59c8e07f
reduced bit widths for integer on fpu
2024-06-20 23:46:45 -07:00
Ross Thompson
249d58244a
It's working!!!!!!
2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
...
Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
David Harris
0ab3f28991
Lint cleanup
2024-06-20 00:10:03 -07:00
David Harris
5f1ee1ac85
Fixed undriven signal in certain config
2024-06-19 15:12:35 -07:00
David Harris
9922b24cbe
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-06-19 14:13:08 -07:00
Ross Thompson
685f4d3807
Removed the last of the ***.
2024-06-19 14:00:31 -07:00
Ross Thompson
7f0ba87231
Updated comments in uart.
2024-06-19 13:51:30 -07:00
Ross Thompson
91c844ca45
Removed more *** from camline and csrc.
2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59
Moved the *** from trap to an issue.
2024-06-19 12:31:24 -07:00
Ross Thompson
9b6b6617af
Cleaned up hptw.
2024-06-19 12:02:56 -07:00
Ross Thompson
24916d42e2
Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw.
2024-06-19 11:40:02 -07:00
Ross Thompson
71f267a17a
Added InstrUpdateDAF to the HPTW.
2024-06-19 11:09:49 -07:00
Ross Thompson
77523c52c2
LSU no longer has ***.
2024-06-19 10:56:07 -07:00
