bbracker
1f52a2f938
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
Ross Thompson
4c0cee1c19
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
David Harris
39bd7e7edc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 07:53:30 -04:00
David Harris
5c2f774c35
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
bbracker
44a48cf28d
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
Ross Thompson
94c3fde724
Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache.
2021-07-08 18:03:52 -05:00
Ross Thompson
93aa39ca31
completed read miss branch through dcache fsm.
...
The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
4f1a85ca7c
Eliminate reserved bits from TLB RAM
2021-07-08 17:35:00 -04:00
David Harris
38772de21f
Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram
2021-07-08 16:58:11 -04:00
David Harris
1190729896
TLB cleanup to match diagrams
2021-07-08 16:52:06 -04:00
Ross Thompson
910ddb83ae
This d cache fsm is getting complex.
2021-07-08 15:26:16 -05:00
Ross Thompson
1fe06bc670
Partial implementation of the data cache. Missing the fsm.
2021-07-07 17:52:16 -05:00
David Harris
5d5274ec73
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b
Renamed tlb ReadLines to Matches
2021-07-07 06:32:26 -04:00
Abe
84711fbdc8
Updated MISA defining as well as porting sizes for peripherals (34 to 56)
2021-07-07 02:37:09 -04:00
Abe
b757c96b2d
Changed SvMode to SVMode on line 76
2021-07-06 23:28:58 -04:00
David Harris
af619dcd75
Added ASID matching for CAM
2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd
more TLB name touchups
2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908
fixed upper bits page fault signal
2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972
connected signals in tlb by name instead of .*
2021-07-06 17:22:10 -04:00
David Harris
ee3a321002
changed tlbphysicalpagemask to structural
2021-07-06 17:16:58 -04:00
David Harris
f960561cbb
changed tlbphysicalpagemask to structural
2021-07-06 17:08:04 -04:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
Ross Thompson
412691df2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
bbracker
d3dd70e3e6
more completely uncomment MMU tests to make sim wally work
2021-07-06 14:33:52 -04:00
Abe
8854532a79
Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)
2021-07-06 12:37:58 -04:00
Ross Thompson
7af8cfba18
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 10:41:45 -05:00
Ross Thompson
6e7e318396
Fixed bug in the LSU pagetable walker interlock.
2021-07-06 10:41:36 -05:00
David Harris
b4082ba776
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 10:44:17 -04:00
David Harris
30fdd7abc8
Cleaned up tlb output muxing
2021-07-06 10:44:05 -04:00
David Harris
d58cad89a8
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
2021-07-06 10:38:30 -04:00
Kip Macsai-Goren
7e9961cac4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 10:16:34 -04:00
David Harris
694badcc6b
Created tlbcontrol module to hide details
2021-07-06 03:25:11 -04:00
David Harris
f805aea236
Implemented TSR, TW, TVM, MXR status bits
2021-07-06 01:32:05 -04:00
David Harris
8b23162d6d
Fixed adrdecs to use Access signals for TIMs
2021-07-05 23:42:58 -04:00
David Harris
71711c54c9
Don't generate HPTW when MEM_VIRTMEM=0
2021-07-05 23:35:44 -04:00
David Harris
179c8d3ed4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-05 23:23:17 -04:00
David Harris
6bac566bb7
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
Ross Thompson
530ddd667b
Fixed combo loop in the page table walker.
2021-07-05 16:37:26 -05:00
Ross Thompson
2a62ee2e70
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-05 16:07:27 -05:00
Kip Macsai-Goren
20cd0e208b
added new mmu tests to makefrag and commented out in the testbench
2021-07-05 10:54:30 -04:00
David Harris
5f91b339aa
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 10:30:46 -04:00
David Harris
ac163e091c
Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported
2021-07-04 19:33:46 -04:00
David Harris
004cac91e1
Simplified PLIC with generate
2021-07-04 19:17:15 -04:00
David Harris
0aae58abed
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 19:02:56 -04:00
David Harris
600e7802dd
Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb
2021-07-04 18:56:30 -04:00
David Harris
db5a06beaf
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:55:24 -04:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
bbracker
287935c09d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:17:16 -04:00
David Harris
07f2064c19
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
bbracker
ceac0352f7
ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF
2021-07-04 18:17:06 -04:00
Ross Thompson
b2c5c3f637
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 17:07:57 -05:00
David Harris
b0f199b574
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
Ross Thompson
02721c29dc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:54:31 -05:00
Ross Thompson
17f37f21ff
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:53:16 -05:00
David Harris
8b707f7703
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:53:08 -04:00
David Harris
80666f0a71
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
Ross Thompson
a252416535
Removed the TranslationVAdrQ as it is not necessary.
2021-07-04 16:49:34 -05:00
bbracker
7191c03282
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 17:20:55 -04:00
bbracker
9c84ab436a
for GPIO give priority to clearing interrupts
2021-07-04 17:20:16 -04:00
Ross Thompson
7f62808544
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
David Harris
07ef67e537
Restructured TLB Read as AND-OR operation with one-hot match/read line
2021-07-04 17:01:22 -04:00
David Harris
8337d6df68
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
2021-07-04 16:33:13 -04:00
David Harris
c281539f36
TLB cleanup
2021-07-04 14:59:04 -04:00
Ross Thompson
5b70eb86b0
relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
2021-07-04 13:49:38 -05:00
David Harris
81742ef9e2
TLB cleanup
2021-07-04 14:37:53 -04:00
David Harris
152923e552
TLB minor organization
2021-07-04 14:30:56 -04:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
1b39481a16
TLB mux and swizzling cleanup
2021-07-04 12:53:52 -04:00
David Harris
735f3b4217
Replaced generates with arrays in TLB
2021-07-04 12:32:27 -04:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
ccd9c05303
Switched to array notation for pmpchecker
2021-07-04 10:51:56 -04:00
David Harris
accbebfa6f
Commented out some unused modules
2021-07-04 01:40:27 -04:00
David Harris
e90c532258
Merge conflict on linux-waves.do
2021-07-04 01:22:10 -04:00
David Harris
9645b023c9
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
bbracker
d68791a6d9
optionally output GDB-formatted instruction list to main buildroot folder
2021-07-03 17:25:19 -04:00
Ross Thompson
9f16d08d0d
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
Ross Thompson
043f1e10c5
Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser.
2021-07-03 15:51:25 -05:00
Ben Bracker
d8facacef6
src/cache/ICacheCntrl.sv
2021-07-03 11:24:41 -05:00
Ben Bracker
eff5a1b90f
fix ICache indenting
2021-07-03 11:11:07 -05:00
David Harris
1fa4abf7b6
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
David Harris
d44916dacf
Cleaned up PMA/PMP checker unused code
2021-07-03 02:25:31 -04:00
Ben Bracker
59b177beac
stop busybear from hanging
2021-07-02 17:22:09 -05:00
David Harris
0bd18ff662
Fixed PMPCFG read faults
2021-07-02 17:08:13 -04:00
Ross Thompson
cf688bd3f6
Fixed up the physical address generation for 64 bit page table walker.
2021-07-02 15:49:32 -05:00
Ross Thompson
8e3149517a
Fixed up the bit widths on the page table walker for rv32.
2021-07-02 15:45:05 -05:00
Ross Thompson
7b3716c281
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
Katherine Parry
20d6e57aa5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-02 12:56:53 -04:00
Katherine Parry
308c9ccaac
FPU update - missing files
2021-07-02 12:53:05 -04:00
Ross Thompson
dbd33465e1
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
David Harris
5b6ebd7935
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-02 12:52:20 -04:00
Katherine Parry
30ff212ca8
FPU update
2021-07-02 12:40:58 -04:00
David Harris
76a43eb468
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:05:25 -04:00
David Harris
c85e0df1ff
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
d1a366472f
reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first.
2021-07-01 18:04:43 -05:00
Ross Thompson
118dfa9cec
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
61027f650c
OMG. It's working!
2021-07-01 17:37:53 -05:00
Ross Thompson
6916784354
Fixed tab space issue.
2021-07-01 17:17:53 -05:00
Ross Thompson
2dc349ea6f
Fixed the wrong virtual address write into the dtlb.
2021-07-01 16:55:16 -05:00
Teo Ene
ec21126474
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
Ross Thompson
88a18496cf
Got some stores working in virtual memory.
2021-07-01 12:49:09 -05:00
Ross Thompson
157b1b31bf
Icache ITLB interlock fix.
2021-06-30 19:24:59 -05:00
Ross Thompson
002c32d2ad
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
bbracker
751e606fb7
trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug
2021-06-26 08:30:58 -04:00
bbracker
17afd9e5e8
temporarily disable PMP checking for EBU accesses.
2021-06-26 07:19:51 -04:00
bbracker
74833dc68c
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
Ross Thompson
d80ebab941
AMO and LR/SC instructions now working correctly.
...
Page table walking is not working.
2021-06-25 15:42:07 -05:00
Ross Thompson
57a7074800
Some progress. Had to change how the page table walker got it's ready.
2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341
Working through a combo loop.
2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
34dbad967d
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
192171826b
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Kip Macsai-Goren
d7e518991e
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Katherine Parry
7e3483b283
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
...
This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
Ross Thompson
6bab454b17
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
bbracker
2d9c91096b
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
53d545cdfe
regression can overcome the fact that buildroots UART prints stuff
2021-06-24 02:00:01 -04:00
bbracker
cee468b21a
whoops meant to remove notifications from busybear, not buildroot
2021-06-24 01:54:46 -04:00
bbracker
13df69abdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-24 01:42:41 -04:00
bbracker
be962cb1ff
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
286b4b5b26
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Katherine Parry
8eed89616c
fpu clean-up
2021-06-23 16:42:40 -04:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
349f6a9471
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-23 09:34:42 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
David Harris
6be0a3b8df
renamed dmem to lsu and removed adrdec module from pmpadrdec
2021-06-22 23:03:43 -04:00
bbracker
fc851ca795
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-22 18:28:30 -04:00
bbracker
303f8e2a7f
give EBU a dedicated PMA unit as just an address decoder
2021-06-22 18:28:08 -04:00
Ross Thompson
67cf2e1c90
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-22 15:47:16 -05:00
Katherine Parry
353a27f12f
rv64f FLW passes imperas tests
2021-06-22 16:36:16 -04:00
