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360 Commits

Author SHA1 Message Date
Ross Thompson
87ed6d510c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
2b891196d9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 16:20:53 -05:00
Noah Boorstin
3c5be59e9b busybear: add branch preditor loading to do file 
(sorry to add more loading to the do instead of less)
 2021-03-05 21:01:41 +00:00
Thomas Fleming
be6ee84d87 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Noah Boorstin
86142e764a Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
889d2c0b85 fix wally-pipelined-batch.do to match wally-pipelined.do 2021-03-05 20:27:01 +00:00
bbracker
850a2e9329 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
77e2e357a7 more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
ed4ff1ecd0 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
19fc7d2381 refactored sim file 2021-03-05 14:25:16 -05:00
bbracker
0f4a231543 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Noah Boorstin
1a11b60664 busybear: slight testbench update 2021-03-05 19:00:40 +00:00
Thomas Fleming
2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4 busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Noah Boorstin
5a3ba1174e busybear: better implenetation of sim-busybear-batch 2021-03-05 00:39:03 +00:00
Ross Thompson
a662aa487c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Ross Thompson
264480f258 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
cfac6bf0c7 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996 fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46 fixed various bugs 2021-03-04 22:18:19 +00:00
Thomas Fleming
3303a013ef Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
735c6789ea busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7 Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Shreya Sanghai
246dbd05e7 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
bbracker
448cba2a5b JALR testing 2021-03-04 10:37:30 -05:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Teo Ene
06be82fc67 Added stop to coremark_bare testbench 2021-03-04 07:47:07 -06:00
Teo Ene
8f1584ca04 Edited assemby of bare-metal coremark to make it run 2021-03-04 07:45:40 -06:00
Teo Ene
396dc61564 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
6ebb79abe0 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
2e409f2299 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
5f98c932bf Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
f060f6cb9d Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
Teo Ene
08a7f6ec25 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches 2021-03-04 01:27:05 -06:00
Thomas Fleming
d9f396ee0e Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
347275e7ee Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Teo Ene
6031269de8 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Thomas Fleming
394051c02f Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Thomas Fleming
d8ac9034b7 Create virtual memory ad-hoc test 
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
 2021-03-03 17:06:37 -05:00
Teo Ene
4562c61af3 Fix to last push 2021-03-03 15:20:38 -06:00
Teo Ene
37bf3d836f Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e6044b9867 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-02 17:23:44 -06:00
Teo Ene
e7f7f980b3 Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
Noah Boorstin
21b1c4163c busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
Noah Boorstin
62b441f3f5 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
965d48afe7 busybear: only check pc when it actually changes 2021-03-01 19:08:35 +00:00
Noah Boorstin
4833b36535 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
David Harris
9bcddfa5dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
2543c29839 Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db Properly implemented the fix from commit 31c07b2adc 2021-02-28 22:22:04 -06:00
Noah Boorstin
bcc0010498 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
f306d2d2e1 busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
db86d20d11 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Noah Boorstin
a03796a519 busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
Noah Boorstin
6e70ae8b3d busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
e5e345d161 busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
c7863d58cd merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
ab9247d625 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
kaveh Pezeshki
ad631ec3a1 fixed sensitivity list on error checking always block, removed useless once and for all 2021-02-26 13:41:16 -05:00
kaveh pezeshki
d32421822c restored 2021-02-26 02:22:08 -08:00
David Harris
b16846bddb Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
24f767a404 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
David Harris
c060e427f0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1 FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84 Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
31c07b2adc Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
Teo Ene
61b872a3e8 Changed TIMBASE in coremark config file 2021-02-25 11:03:41 -06:00
Teo Ene
c47872c2af Changed .do file back to run all 2021-02-25 09:58:54 -06:00
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
3e5de35fc4 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
kaveh pezeshki
3bb8e0d918 condensed always blocks to avoid race conditions 2021-02-24 11:35:28 -08:00
Noah Boorstin
3d82ceffb7 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
David Harris
f5e9c91193 All tests passing with bus interface 2021-02-24 07:25:03 -05:00
kaveh pezeshki
b36a5614b4 added comments for RAM and bootram, removed trailing whitepace 2021-02-23 21:28:33 -08:00
Noah Boorstin
c8e9edcc43 busybear: add bootram section in the same manner as ram 2021-02-24 02:02:28 +00:00
Noah Boorstin
a24270c4ca busybear: add support for subwords in ram 
this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
 2021-02-24 01:51:18 +00:00
Noah Boorstin
00605864fc busybear: start adding ram 2021-02-23 22:01:23 +00:00
Katherine Parry
8f5cc19143 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
7b103423e1 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
d5e7a8a4cf busybear: remove unused signals 2021-02-23 19:38:19 +00:00
Noah Boorstin
ceb7df3561 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
817f81c356 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
9b3637bd87 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
f25de68b7d minor change to wave file. 2021-02-19 09:08:13 -06:00
Ross Thompson
c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Thomas Fleming
21552eaf9d Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
acd7ba8b60 Updated creation date of mul 2021-02-18 08:13:08 -05:00
Ross Thompson
de9e383bc6 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 
Once combined with some simulation verilog this will display the current function in modelsim.
 2021-02-17 22:20:28 -06:00
Ross Thompson
5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
2f5b4c3a25 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
64536dbc34 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00
David Harris
dc758a0c7b Multiplier tweaks 2021-02-17 16:00:27 -05:00
David Harris
3edf910c18 Started to integrate OSU divider 2021-02-17 15:38:44 -05:00
David Harris
cb0054b524 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
8dec69c2ce Added MUL 2021-02-15 22:27:35 -05:00
Ross Thompson
78db3654c6 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 
This is not yet tested but the system verilog does compile.
 2021-02-15 14:51:39 -06:00
David Harris
f00728448a WALLY ALU tests 2021-02-15 10:16:31 -05:00
David Harris
37dba8fd26 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Domenico Ottolia
75d9091fe8 Add privileged test cases 2021-02-14 17:01:46 -05:00
Ross Thompson
3ec1f668fc added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. 2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. 2021-02-14 11:06:31 -06:00
Shreya Sanghai
30bfd7534c added branch tests 2021-02-12 22:40:08 -05:00
Noah Boorstin
7312da1a99 busybear: allow testbench to ignore lack of MMU for now 
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing

If it is, we're at 1M instructions!
 2021-02-12 20:08:56 +00:00
Noah Boorstin
97302dd12f busybear: slightly neater error handling 2021-02-12 17:21:56 +00:00
bbracker
9231646fb3 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Noah Boorstin
5bf6add635 bump into virtual/physcial memory? 2021-02-11 23:06:12 -05:00
Noah Boorstin
4427780a41 busybear: more updates 
now gets to instruction 839037 before failing
also updates to match new gdb output format

umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
 2021-02-11 22:42:58 -05:00
Tejus Rao
5158ca4220 added test cases for ADDW, SUBW, SLLW, SRLW, SRAW 2021-02-11 13:38:38 -05:00
Teo Ene
8a6de4fb86 Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
ethan-falicov
9edc4b6bfe Fixed merge conflict stuff 2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a More merge conflicts yay 2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7 Merge conflict fixing 2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0 Adding I Type test cases from Lab 1 2021-02-10 09:39:43 -05:00
David Harris
183a2dcfb5 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
63c7c18771 Fixed lw by delaying read value by one cycle 2021-02-07 23:28:21 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
Jarred Allen
403a0d033c Fix compile error in imperas testbench 2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74 merge conflict? 2021-02-07 02:34:49 -05:00
Noah Boorstin
01c0f9db63 Busybear: next week of updates 
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
 - parsed first 1M instructions, and now parse from split GDB runs
 - now at about 230k instructions, can't progress further for now since atomic instructions
   aren't implemented yet
 2021-02-07 03:14:48 +00:00
Jarred Allen
48ade25577 Actually run the WALLY-LOAD tests 2021-02-06 14:56:40 -05:00
Jarred Allen
edd758453e Add test vector set for load instructions 2021-02-06 13:05:59 -05:00
bbracker
691d651fde JAL testing 2021-02-05 08:08:42 -05:00
Noah Boorstin
14cde0d59c Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Thomas Fleming
8588a1ed6b Complete STORE tests 2021-02-04 15:38:22 -05:00
Noah Boorstin
dc881bd51b busybear: add more CSRs 2021-02-04 20:13:36 +00:00