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734 Commits

Author SHA1 Message Date
Madeleine Masser-Frye
a54837b102 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
655266a216 Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
a64e65e54c Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
dd33f2a009 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
be658d3933 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
571eb21f41 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
38382e3a11 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
a5aa75e5de Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
b53aef33f5 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
cc06fa1c55 Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
f81719337e Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
slmnemo
85801e75db Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
90c5e5d319 Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
Katherine Parry
eb93bd46d7 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Madeleine Masser-Frye
2383ca4f53 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
6c6a12cfd5 added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
5ae63f913a fixed compilation errors 2022-06-03 15:34:17 +00:00
Katherine Parry
c5bde75e30 added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
ccda4c771e fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
David Harris
9065b684f8 Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
7cf5d481c0 Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
129fab3794 Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
Katherine Parry
74b549ddc8 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
Katherine Parry
707067548f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
108f32e9df Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
slmnemo
56121b3587 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
2b80788235 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
c24f88c2e9 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
efe4b3e8fe Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
99da6537cc Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
79df271a6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
31815422d2 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
Katherine Parry
cd7fe9af61 reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
559c0c278e added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
2935188035 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
d1ef3b8981 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
835a4e4606 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
f426850bc7 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
80315fedff fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4335895b21 Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
822866fd0a removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
d5c249bf71 unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
3c63db9554 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
b288f812ab moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
efb972c6d3 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bddc32ed21 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00
slmnemo
efce3e4953 added LSUBurstDone signal to signal when a burst has finished 2022-05-26 16:29:13 -07:00
Katherine Parry
550c4d380c fcvt.sv paramaterized 2022-05-26 20:48:22 +00:00
slmnemo
ae460eccd4 Added signal to monitor HBURST and comments for each burst in busdp 2022-05-26 13:35:49 -07:00
slmnemo
80965f953c added burst size signals to the IFU, EBU, LSU, and busdp 2022-05-25 18:02:50 -07:00
slmnemo
95d64fe4ae idk lol it says this has an unadded change 2022-05-25 17:17:49 -07:00
Katherine Parry
f4b9ade942 added fcvt.sv 2022-05-26 00:10:51 +00:00
Katherine Parry
c264585fe8 single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
c8892f2847 ppaAnalyze: docstrings and tsmc28 plotting 2022-05-25 13:52:20 +00:00
Madeleine Masser-Frye
7d1448d2ad added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
Ross Thompson
1dde9db2ce Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 23:54:33 -05:00
Ross Thompson
13f7f48776 Possible plic fix? 2022-05-22 23:47:01 -05:00
Madeleine Masser-Frye
99aa110615 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-22 23:23:39 +00:00
Madeleine Masser-Frye
378523087f added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Ross Thompson
ff8e158ec4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-22 10:55:33 -05:00
Ross Thompson
848abf29b5 Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Madeleine Masser-Frye
0bcae85792 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-05-21 09:53:31 +00:00
Madeleine Masser-Frye
fcaf032a0d ppa updates 
added widths to modules, automated frequency sweep synthesis, added slack violation color coding to plots
 2022-05-21 09:53:26 +00:00
Katherine Parry
6bc31f2e78 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
slmnemo
4a2538455d added documentation for ahblite burst types to ahblite.sv 2022-05-19 18:31:46 -07:00
Katherine Parry
bc4804d90a fixed lint warning 2022-05-19 20:34:06 +00:00
Katherine Parry
b0881495a9 Bug fixed in unpacker and sub/add/mul tests pass TestFloat 2022-05-19 20:31:23 +00:00
mmasserfrye
b255f61521 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-19 20:24:57 +00:00
mmasserfrye
710905b239 updated synth plotting and regression 2022-05-19 20:24:47 +00:00
Katherine Parry
cc0ab94ebc Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
mmasserfrye
1442afe4e2 added support for plotting and fitting power 2022-05-18 17:01:55 +00:00
mmasserfrye
0265d1988e adapted shifter in ppa.sv for widths beside 32 and 64 
modified plotting and regression in ppaAnalyze.py
 2022-05-18 16:08:40 +00:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
mmasserfrye
43cf4f35cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-17 01:11:58 +00:00
mmasserfrye
24420dea6c added 8 and 128 bit versions, adjusted alu 2022-05-17 01:11:43 +00:00
slmnemo
c84731d6d0 Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
mmasserfrye
c8e43e9798 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
resolved merge conflict
 2022-05-16 15:42:59 +00:00
mmasserfrye
2ca897620f tuning modules for ppa 2022-05-16 15:39:15 +00:00
David Harris
f5e2cff45a Cause simplification 2022-05-12 23:47:21 +00:00
David Harris
6303d4e81f Cause simplification 2022-05-12 23:39:10 +00:00
David Harris
c4621c5b6b Cause simplification 2022-05-12 23:37:40 +00:00
David Harris
7daf631c13 Cause simplification 2022-05-12 23:33:35 +00:00
David Harris
de51c7eeb3 Cause simplification 2022-05-12 23:33:22 +00:00
David Harris
803bfc4fe4 Cause simplification 2022-05-12 23:29:35 +00:00
David Harris
2d27d20db9 Cause simplification 2022-05-12 23:27:02 +00:00
David Harris
87dadc8208 trap/csr cleanup 2022-05-12 22:26:21 +00:00
David Harris
ea0d9fd9a8 More trap/csr simplification 2022-05-12 22:06:03 +00:00
David Harris
2eb6a65fa2 More trap/csr simplification 2022-05-12 22:04:20 +00:00
David Harris
2d8ccbd4ea More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
417e36bff5 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
ca6b7716e2 Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
56c154f2e7 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
730bcac6ba Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
c5868b81e4 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
517e44746e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
2675c217e0 cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
5537c33196 Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
57a69d0f67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
30a1ba7bcf renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
449472ba58 Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
9f8dca5190 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1d01bc98a4 Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
21c1e58829 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
61199ccd13 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
4c5e361b00 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5acb526375 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
7e764fbda1 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
e2dea3bb89 Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
fb725a9e0a Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
8372bc86a7 Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
15659b05e4 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
877c4eefd1 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
cf900cf44d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
52b0e7d567 filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
32f8841f79 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
c738c130de merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
e37d262e4c PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
70fe1184db ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
a8c9f504fa Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
91472eb948 Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
91b786c58d Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
d53e4b1b1f Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
b869190161 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
8066ba45e8 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
2792d77e4e Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
2cdd49c7d2 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
7024293a59 Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
66424a8246 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
866540580a SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
94459ade3d Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
David Harris
8eee0c0ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
554c2b3550 Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
cb1a7d54a4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
4fbf78e049 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
9c4de0e9c1 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
dee32f70bf Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
bc123b5564 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
7e3f75a35d Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20 sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
David Harris
6e8b27de17 Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
ffd4713fd1 Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9042844b38 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
8ad920fcb3 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
David Harris
cf1fde62fb Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
0ede295e88 Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
851d5e8c5e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
16ad1e0cab Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
f1ddbb169c Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
03f84bf11c Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
7bc6943527 Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
afc38abe08 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
David Harris
5c607f2b6b Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
David Harris
1f7a95637a Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
a8ad7be246 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
1ba328324b Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Shreya Sanghai
fd3920b217 replaced k with bpred size 2022-04-18 04:21:03 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
David Harris
4a7effaf9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
David Harris
2819a1c305 Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00
David Harris
812b56acc6 Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
de5b61291f Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
Ross Thompson
059c04e2a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-17 15:23:46 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
David Harris
2436534687 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
David Harris
83d283354c Added comments in fcvt 2022-04-17 16:53:10 +00:00
David Harris
aa1bac361d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
16b3c64234 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-16 14:59:03 -05:00
Ross Thompson
b9a19304db Fixed possible bugs in LRSC. 2022-04-16 14:45:31 -05:00
David Harris
68d9c99fba Added WFI support to IFU to keep it in the pipeline 2022-04-14 17:26:17 +00:00
David Harris
855d68afde WFI should set EPC to PC+4 2022-04-14 17:05:22 +00:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
ab9738d3be Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
2294cbc1c6 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Katherine Parry
c307cff503 fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
Ross Thompson
9517fe9faf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Katherine Parry
20885f4dea generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
0ed34b8e63 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
0806d1a134 Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
d83db2cde5 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
fd9a33e453 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
David Harris
6966554ee8 Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
Ross Thompson
d135866098 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-02 16:39:54 -05:00
Ross Thompson
5ef6cde52e Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
f58a1eff9e Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
178ecaa451 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
0340c0fd44 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
bbracker
36c30b14c1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
e60139d3ee fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
cb945a6a6a Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
1586f893b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
7e05935348 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
e81f317764 Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
d32e1147bf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
34c94f150e simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
2ed1c9f14f Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
fb0eec0f76 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
0942429b7f Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
a6d090a7c0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
dc48d84dd6 Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
93d6b2fb62 Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
f917ed7ed0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
bbracker
54b9745a75 big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
b2a77da96b Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
44f94173bf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
Ross Thompson
3ac736e2d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
370a075fa1 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
1993069986 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
fc2b4453ec rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
de2672231d Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
David Harris
057ee56d7e Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
049c55769a fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
ad106e7130 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
bbracker
46ffa4b079 fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Kip Macsai-Goren
dc9635b757 fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Ross Thompson
7099259ff7 I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit. 2022-03-25 13:10:31 -05:00
Ross Thompson
7a824eaae1 Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB. 2022-03-24 23:47:28 -05:00
bbracker
150a7b234b tabs vs spaces disagreement 2022-03-24 17:11:41 -07:00
bbracker
9f60256f22 1st attempt at multiple channel PLIC 2022-03-24 17:08:10 -07:00
Ross Thompson
58668812c1 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
Ross Thompson
07b7dbc922 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-23 14:10:38 -05:00
Katherine Parry
abdbc31d14 fixed typo in unpack.sv 2022-03-23 18:26:59 +00:00
Katherine Parry
ead88fba55 fixed lint error in fpudivsqrtrecur.sv 2022-03-23 03:24:41 +00:00
Ross Thompson
6ab14d7302 Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing. 2022-03-22 22:04:06 -05:00
Ross Thompson
c5be2cb1d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-22 21:28:50 -05:00
Katherine Parry
c3c764a171 unpack.sv cleanup 2022-03-23 01:53:37 +00:00
Ross Thompson
cec7625d91 Added comment about needed fix to misaligned fault. 2022-03-22 16:52:07 -05:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
d347de8c49 dtim writes are supressed on non cacheable operation. 2022-03-12 00:46:11 -06:00
Ross Thompson
d8947fa616 cleanup of ram.sv 2022-03-11 18:09:22 -06:00
Ross Thompson
e802deb4d6 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
81a2fbb6d2 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
04dd2f0eb5 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
a598760445 Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
5c16b65a16 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00