cvw/pipelined/src
2022-06-08 15:29:32 -07:00
..
cache Removing unused signals 2022-05-12 14:36:15 +00:00
ebu Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
fpu fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
generic Cleaned bram interface 2022-06-08 01:39:44 +00:00
hazard Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
ieu Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
ifu Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
lsu Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
mmu Clean up unused signals 2022-05-12 14:49:58 +00:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
privileged Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
uncore Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
wally Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00