bbracker
9bc5ddf5f2
PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
2021-06-17 05:19:36 -04:00
bbracker
7b98e7aa2f
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
bbracker
cd00e04943
Merge remote-tracking branch 'origin/fixPrivTests' into main
2021-06-15 09:57:46 -04:00
Katherine Parry
4177f4f148
Updated FMA
2021-06-14 13:42:53 -04:00
David Harris
c6ff11c22e
disabled Verilator WIDTH warnings in ICCacheCntrl
2021-06-12 19:50:06 -04:00
Ross Thompson
294f01cbd8
fixed the mtime register.
2021-06-11 13:50:13 -05:00
James E. Stine
11c88c15d5
Put repository of fpdivsqrt with RTL-based adder instead of structural implementation
2021-06-11 14:35:22 -04:00
David Harris
49b5fa3994
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
David Harris
e41a87be23
Restored counter events
2021-06-10 11:18:58 -04:00
David Harris
d386929c0e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-10 10:47:55 -04:00
David Harris
802238643a
Removed two cycles of latency from the DTIM
2021-06-10 10:30:24 -04:00
bbracker
f272cd46d8
peripheral lint fixes
2021-06-10 10:19:10 -04:00
bbracker
d4aeb1c387
merge
2021-06-10 10:03:01 -04:00
bbracker
79e798a641
UART improved and added more reg read side effects
2021-06-10 09:53:48 -04:00
David Harris
3e8026dc21
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
75870a16d7
Restored PCCorrectE declaration in IFU
2021-06-09 21:09:16 -04:00
David Harris
0ffbd03139
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
90e5781471
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
David Harris
b613f46c2d
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
Kip Macsai-Goren
aab7bd94f7
Merge small mmu changes into main
2021-06-08 14:00:26 -04:00
Kip Macsai-Goren
d6f47d5917
making mmu branch line up with main
2021-06-08 13:59:03 -04:00
Kip Macsai-Goren
e209dbcf50
some cleanup of signals, not done yet
2021-06-08 13:39:32 -04:00
bbracker
cc91c774a6
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
e7e4105931
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
49515245d9
remove redundant decodes, fixed mmu logic ins/outs
2021-06-07 19:23:30 -04:00
Kip Macsai-Goren
1e174a8244
got rid of some underscores in filenames, modules
2021-06-07 18:54:05 -04:00
Kip Macsai-Goren
c96695b1b6
implemented simpler page mixers, cleaned up a bit
2021-06-07 18:32:34 -04:00
Kip Macsai-Goren
b27abc53e8
began updating cam line to reduce muxes, confusion
2021-06-07 17:03:31 -04:00
Kip Macsai-Goren
6a63ad04d2
regression working partially done page mask
2021-06-07 17:02:31 -04:00
David Harris
9efbffdee5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-07 16:14:13 -04:00
David Harris
43a690dc42
Simplified superpage matching
2021-06-07 16:11:28 -04:00
Katherine Parry
0acf665a8b
lint is clean
2021-06-07 14:22:54 -04:00
David Harris
2ae5ca19b5
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
dc0b19dfaa
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
d5ec797ba4
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Katherine Parry
75a6097467
fixed lint warnings for fpu and lzd
2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
49200bd922
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
22e8e06ac7
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
037aa6fa89
Merge branch 'mmu' into main
...
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
2021-06-04 17:07:56 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Ross Thompson
41a1e6112a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-04 15:16:39 -05:00
Ross Thompson
7406e33b61
Continued I-Cache cleanup.
...
Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
Ross Thompson
191f7e61fd
Moved I-Cache offset selection mux to icache.sv (top level).
...
When we switch to set associative this is will be more efficient.
2021-06-04 13:49:33 -05:00
Ross Thompson
e0d0fdd708
Cleaned up the I-Cache memory.
2021-06-04 13:36:06 -05:00
Katherine Parry
fc65aedbd6
Double-precision FMA instructions
2021-06-04 14:00:11 -04:00
Ross Thompson
fdef8df76b
Reorganized the icache names.
2021-06-04 12:53:42 -05:00
Ross Thompson
7c44f19925
Relocated the icache to the cache directoy.
2021-06-04 12:23:46 -05:00
David Harris
a26bf37be8
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
0674f5506e
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
bbracker
ad3b103a86
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-03 10:03:26 -04:00
bbracker
4e765ee1c5
expanded GPIO testing and caught small GPIO bug
2021-06-03 10:03:09 -04:00
Ross Thompson
e50a1ef5e4
Fixed a few lint errors,
...
clock gater was wrong,
missing signal definitions in branch predictor.
2021-06-02 09:33:24 -05:00
bbracker
a683dd7fde
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-02 10:03:23 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Kip Macsai-Goren
5187574e8a
implemented Sv48.
2021-06-01 17:50:37 -04:00
James E. Stine
eba7ce64f5
delete div.bak
2021-06-01 17:39:54 -04:00
Ross Thompson
babcea195a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 15:20:37 -05:00
Ross Thompson
0670c57fd2
The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
2021-06-01 15:05:22 -05:00
James E. Stine
564d7c4adb
Minor cosmetic update to fpu.sv
2021-06-01 15:45:32 -04:00
James E. Stine
2eeb12c674
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
fe22fd2db8
added clock gater to floating point divider to speed up simulation time.
2021-06-01 13:46:21 -05:00
Ross Thompson
7f1653f073
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 12:42:21 -05:00
Ross Thompson
997c13a521
Forgot to include the new gshare predictor file.
2021-06-01 12:42:03 -05:00
Kip Macsai-Goren
fac2431add
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-01 13:20:39 -04:00
Ross Thompson
89ad4477e4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-06-01 11:33:12 -05:00
Ross Thompson
857f59ab5c
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
James E. Stine
ddbdd0d5a2
Modify muldiv.sv to handle W instructions for 64-bits
2021-05-31 23:27:42 -04:00
Ross Thompson
f6c88666cf
may have fixed the global branch history predictor.
...
The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired.
2021-05-31 16:11:12 -05:00
Kip Macsai-Goren
0fe63282f8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-31 11:01:15 -04:00
James E. Stine
46a232b862
Cosmetic changes on integer divider
2021-05-31 09:16:30 -04:00
James E. Stine
9954d16fc9
Add enhancements to integer divider including:
...
- better comments
- optimize FSM to end earlier
- passes for 32-bit or 64-bit depending on parameter to intdiv
Left div.bak in just in case have to revert back to original for now.
2021-05-31 09:12:21 -04:00
James E. Stine
12c34c25f3
Modify elements of generics for LZD and shifter wrote for integer
...
divider.
2021-05-31 08:36:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Kip Macsai-Goren
690815ca51
made priority encoder parameterizable
2021-05-28 18:09:28 -04:00
Ross Thompson
8a035104ac
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
Katherine Parry
778ba6bbf5
classify unit created and passes imperas tests
2021-05-27 18:53:55 -04:00
Katherine Parry
1459d840ed
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
309e6c3dc1
FADD and FSUB imperas tests pass
2021-05-26 12:33:33 -04:00
James E. Stine
bb99480fca
delete old file for FPregfile
2021-05-26 09:13:09 -05:00
James E. Stine
77260643eb
Add regression test for fpadd
2021-05-26 09:12:37 -05:00
Katherine Parry
e7190b0690
renamed top level FPU wires
2021-05-25 20:04:34 -04:00
Ross Thompson
fec40a1b75
fixed bug with icache miss spill fsm branch.
2021-05-25 14:26:22 -05:00
James E. Stine
bb5404e14a
Update FPregfile to use more compact code and better structure for ease in reading
2021-05-25 13:21:59 -05:00
Ross Thompson
063e458ff0
Merge remote-tracking branch 'refs/remotes/origin/main' into main
2021-05-24 23:25:36 -05:00
Ross Thompson
16e037b8e9
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
James E. Stine
c4f3f2f783
Minor cosmetic elements on div.sv
2021-05-24 19:30:28 -05:00
James E. Stine
295263e122
Mod for DIV/REM instruction and update to div.sv unit
2021-05-24 19:29:13 -05:00
Ross Thompson
c5310e85c1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-24 14:28:41 -05:00
Katherine Parry
90d5fdba04
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Ross Thompson
65632cb7c9
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
72f77656a3
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
James E. Stine
6f38b7633c
Update header for FPadd
2021-05-24 08:28:16 -05:00
Katherine Parry
70968a4ec3
FSD and FLD imperas tests pass
2021-05-23 18:33:14 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
bf6337f2f7
plic implementation optimizations
2021-05-19 18:10:48 +00:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
James E. Stine
e808b06b82
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
James E. Stine
5506efc115
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
