bbracker 2c77a13c08 fixed InstrValid signals and implemented less costly MEPC loading		2021-06-02 10:03:19 -04:00
..
cache	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
dmem	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
ebu	Clean up MMU code	2021-05-14 07:12:32 -04:00
fpu	classify unit created and passes imperas tests	2021-05-27 18:53:55 -04:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
ieu	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
ifu	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
mmu	Fix comment	2021-05-14 08:06:07 -04:00
muldiv	Minor cosmetic elements on div.sv	2021-05-24 19:30:28 -05:00
privileged	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
uncore	plic implementation optimizations	2021-05-19 18:10:48 +00:00
wally	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00