Ross Thompson 0670c57fd2 The clock gater was not implemented correctly. Now it is level sensitive to a low clock.		2021-06-01 15:05:22 -05:00
..
cache	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
dmem	progress on bus and lrsc	2021-04-26 07:43:16 -04:00
ebu	Clean up MMU code	2021-05-14 07:12:32 -04:00
fpu	added clock gater to floating point divider to speed up simulation time.	2021-06-01 13:46:21 -05:00
generic	The clock gater was not implemented correctly. Now it is level sensitive to a low clock.	2021-06-01 15:05:22 -05:00
hazard	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
ieu	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
ifu	Forgot to include the new gshare predictor file.	2021-06-01 12:42:03 -05:00
mmu	made priority encoder parameterizable	2021-05-28 18:09:28 -04:00
muldiv	Modify muldiv.sv to handle W instructions for 64-bits	2021-05-31 23:27:42 -04:00
privileged	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00
uncore	plic implementation optimizations	2021-05-19 18:10:48 +00:00
wally	turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)	2021-05-28 23:11:37 -04:00