James E. Stine 11c88c15d5 Put repository of fpdivsqrt with RTL-based adder instead of structural implementation		2021-06-11 14:35:22 -04:00
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cache	More verilator fixes, but bpred is broken	2021-06-09 21:03:03 -04:00
dmem	Start to parameterize number of PMP Entries	2021-06-08 15:29:22 -04:00
ebu	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
fpu	Put repository of fpdivsqrt with RTL-based adder instead of structural implementation	2021-06-11 14:35:22 -04:00
generic	fixed lint warnings for fpu and lzd	2021-06-05 12:06:33 -04:00
hazard	lint is clean	2021-06-07 14:22:54 -04:00
ieu	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
ifu	Restored PCCorrectE declaration in IFU	2021-06-09 21:09:16 -04:00
mmu	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
muldiv	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
privileged	Reverted MIDELEG and MEDELEG to XLEN so busybear passes	2021-06-10 23:47:32 -04:00
uncore	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-06-10 10:47:55 -04:00
wally	Start to parameterize number of PMP Entries	2021-06-08 15:29:22 -04:00