cvw/wally-pipelined/src
Ross Thompson 7406e33b61 Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
..
cache Continued I-Cache cleanup. 2021-06-04 15:14:05 -05:00
dmem fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
ebu Clean up MMU code 2021-05-14 07:12:32 -04:00
fpu Fixed a few lint errors, 2021-06-02 09:33:24 -05:00
generic Fixed a few lint errors, 2021-06-02 09:33:24 -05:00
hazard turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
ieu fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
ifu Relocated the icache to the cache directoy. 2021-06-04 12:23:46 -05:00
mmu implemented Sv48. 2021-06-01 17:50:37 -04:00
muldiv delete div.bak 2021-06-01 17:39:54 -04:00
privileged fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
uncore expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
wally fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00