David Harris
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5b6ebd7935
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-02 12:52:20 -04:00 |
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Katherine Parry
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30ff212ca8
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FPU update
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2021-07-02 12:40:58 -04:00 |
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David Harris
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c85e0df1ff
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:04:13 -04:00 |
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Teo Ene
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ec21126474
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Flow updated for 90nm
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2021-07-01 13:32:42 -05:00 |
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Ross Thompson
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157b1b31bf
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Icache ITLB interlock fix.
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2021-06-30 19:24:59 -05:00 |
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Katherine Parry
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0c2b7a1132
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FPU control signals changed and FMA works
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2021-06-28 18:53:58 -04:00 |
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bbracker
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17afd9e5e8
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temporarily disable PMP checking for EBU accesses.
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2021-06-26 07:19:51 -04:00 |
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bbracker
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34dbad967d
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ah merge; I checked and this does pass all of regression except lints
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2021-06-25 07:37:06 -04:00 |
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bbracker
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192171826b
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changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
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2021-06-25 07:18:38 -04:00 |
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Katherine Parry
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7e3483b283
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FPU forwarding reworked pt.1
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2021-06-24 18:39:18 -04:00 |
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bbracker
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2155a4e485
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Revert "fixed forwarding"
This reverts commit 86e369df52.
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2021-06-24 17:39:37 -04:00 |
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bbracker
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86e369df52
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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Katherine Parry
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8eed89616c
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fpu clean-up
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2021-06-23 16:42:40 -04:00 |
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Ross Thompson
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f74ecbb81e
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Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
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2021-06-23 15:13:56 -05:00 |
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Ross Thompson
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349f6a9471
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-23 09:34:42 -05:00 |
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David Harris
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a514554eeb
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Reduced complexity of pmpadrdec
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2021-06-23 03:03:52 -04:00 |
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David Harris
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2060a5c2f8
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Reduced complexity of pmpadrdec
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2021-06-23 02:31:50 -04:00 |
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David Harris
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fa51ab9f68
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Refactored pmachecker to have adrdecs used in uncore
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2021-06-23 01:41:00 -04:00 |
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David Harris
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6be0a3b8df
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renamed dmem to lsu and removed adrdec module from pmpadrdec
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2021-06-22 23:03:43 -04:00 |
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bbracker
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fc851ca795
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-22 18:28:30 -04:00 |
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bbracker
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303f8e2a7f
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give EBU a dedicated PMA unit as just an address decoder
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2021-06-22 18:28:08 -04:00 |
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Ross Thompson
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67cf2e1c90
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-22 15:47:16 -05:00 |
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Katherine Parry
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353a27f12f
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rv64f FLW passes imperas tests
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2021-06-22 16:36:16 -04:00 |
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Kip Macsai-Goren
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7e06a3c04d
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Fixed mask assignment error, made usage, variables more clear
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2021-06-22 13:31:06 -04:00 |
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Kip Macsai-Goren
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2c41da0275
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Continued fixing fsm to work right with svmode
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2021-06-22 13:29:49 -04:00 |
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Kip Macsai-Goren
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3e19eba20d
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updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
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2021-06-22 11:21:11 -04:00 |
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Ross Thompson
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f79e5eaa47
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-21 16:41:09 -05:00 |
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Ross Thompson
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3cbe4c9bc2
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Improved some names in icache.
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2021-06-21 16:40:37 -05:00 |
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David Harris
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5d6dc82db2
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Added Physical Address and Size to PMA Checker/MMU
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2021-06-21 01:27:02 -04:00 |
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David Harris
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1ec90a5e1f
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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David Harris
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d2ec04564b
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Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
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2021-06-20 22:59:04 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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Katherine Parry
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2b67f25683
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all rv64f instructions except convert, divide, square root, and FLD pass
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2021-06-20 20:24:09 -04:00 |
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bbracker
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83a0a37f8e
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make xCOUNTEREN what buildroot expects it to be
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2021-06-20 09:22:31 -04:00 |
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Ross Thompson
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70c45a5349
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Revert "Icache now uses physical lenght bits rather than XLEN."
This reverts commit 16266d978a.
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2021-06-19 08:58:34 -05:00 |
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Ross Thompson
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868ddce5f2
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Revert "Improved some names in icache."
This reverts commit a57c63aa7b.
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2021-06-19 08:58:32 -05:00 |
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Ross Thompson
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a57c63aa7b
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Improved some names in icache.
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2021-06-18 12:22:41 -05:00 |
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Ross Thompson
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16266d978a
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-18 12:02:59 -05:00 |
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David Harris
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580ac1c4df
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Made MemPAdrM and related signals PA_BITS wide
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2021-06-18 09:36:22 -04:00 |
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David Harris
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de221ff2d0
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Changed physical addresses to PA_BITS in size in MMU and TLB
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2021-06-18 09:11:31 -04:00 |
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David Harris
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df7e373c69
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Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX
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2021-06-18 08:13:15 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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David Harris
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de3a0c644b
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Further cleaning of PMA checker
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2021-06-17 22:27:39 -04:00 |
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David Harris
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679e507cc6
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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David Harris
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54b6a2dcad
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added inputs to pmaadrdec
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2021-06-17 18:54:39 -04:00 |
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David Harris
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da8eb7749f
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Started simplifying PMA checker
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2021-06-17 16:28:06 -04:00 |
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bbracker
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2bee4eabab
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added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
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2021-06-17 12:09:10 -04:00 |
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bbracker
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b65adbea63
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enable TIME CSR for 32 bit mode as well
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2021-06-17 11:34:16 -04:00 |
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bbracker
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5a661a7392
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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