James E. Stine e808b06b82 Forgot initialization config for div - apologies		2021-05-17 17:12:27 -05:00
..
cache	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00
dmem	progress on bus and lrsc	2021-04-26 07:43:16 -04:00
ebu	Clean up MMU code	2021-05-14 07:12:32 -04:00
fpu	fpu warnings fixed/commented	2021-05-03 19:17:09 +00:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
ieu	small synthesis fixes	2021-05-04 15:21:01 -04:00
ifu	Fixed synthesis bug with icache valid bit.	2021-05-04 13:03:08 -05:00
mmu	Fix comment	2021-05-14 08:06:07 -04:00
muldiv	Forgot initialization config for div - apologies	2021-05-17 17:12:27 -05:00
privileged	Clean up MMU code	2021-05-14 07:12:32 -04:00
uncore	Rolled back fflush on uart. Use -syncio in Modelsim command line instead.	2021-05-03 20:04:44 -04:00
wally	Remove busy-mmu and fix missing signal	2021-05-14 07:14:20 -04:00