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425 Commits

Author SHA1 Message Date
Rose Thompson
9703055758 The FPGA is synthesizing with the rvvi and ethernet hardware. 2024-05-30 15:37:17 -05:00
Rose Thompson
8123695831 Maded insert_debug_comment.sh compatible with cygwin. 2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301 Fixed fpga to work with the updated regression changes. 2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608 Fixed insert_debug_comment.sh to work with the older version of bash. 2024-04-16 10:55:26 -05:00
Rose Thompson
6097444b5a Added missing file for compiling the fpga zero stage bootloader. 2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db Moved the zero stage boot loader to the fpga directory. 2024-03-01 10:23:55 -06:00
Rose Thompson
cc7f433ce0 Update the fpga scripts to use the new derivative configs. 2024-01-31 13:19:28 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
7693c5d4e2 Updates to fpga top level. 2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388 Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c Replaced fpga top level verilog with system verilog. 2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3 Get's the fpga building again after the git history rewrite. 2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile. 2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12 Modified FPGA Makefile to override with relative path. FPGA boots now. 2023-11-30 17:51:15 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
cdd21d6635 Added menvcfg to debugger for checking what linux has configured. 2023-11-19 13:44:22 -06:00
Jacob Pease
87e6a5ccf2 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
Jacob Pease
ff73f798ed Replaced vivado-risc-v addins directory with new SDC repo. 2023-11-16 13:59:12 -06:00
Rose Thompson
d4bc9da085 Fixed another bug in the updated script changes. 2023-11-13 18:12:02 -06:00
Rose Thompson
f8b65f50b0 Fixed bugs in the updated fpga synthe script. 2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90 Modified the fpga build script to generate it's own config file rather than use the one in config/fpga. 2023-11-13 17:48:28 -06:00
Rose Thompson
6b7ff50a84 Reduced Arty A7 clock speed to 20Mhz to support Zicclsm. 2023-11-13 16:44:02 -06:00
Ross Thompson
d33c966a42 Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00
Ross Thompson
055e00b8ac Pushed vcu118 to 71MHz. 2023-08-25 17:04:50 -05:00
Jacob Pease
2bf6207919 Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
Jacob Pease
e489ede51d Merge branch 'main' of github.com:openhwgroup/cvw 2023-08-21 16:10:09 -05:00
David Harris
d801916d97 Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
Ross Thompson
a16cde3dc6 Removed unused file. 2023-08-21 15:12:59 -05:00
Ross Thompson
1e0f1aeeac Updated artyA7 debugger to match book. 2023-08-21 14:35:42 -05:00
Jacob Pease
144d93eba4 Added SPDX headers to other probe scripts. 2023-08-16 14:04:25 -05:00
Jacob Pease
f91157fc95 Added SPDX header to probe script. 2023-08-16 13:05:37 -05:00
Jacob Pease
c2f2bef433 Fixed bug caused by errant tab size in probe script. 2023-08-16 12:20:08 -05:00
Jacob Pease
63e901e981 Added probe script to generate a single probe for the fpga. 2023-08-16 12:12:31 -05:00
Ross Thompson
cab40e618f Updateds to vcu118 constraints and device tree. 2023-08-02 16:51:32 -05:00
Ross Thompson
fb1c1a1832 Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails. 2023-08-02 16:14:04 -05:00
Ross Thompson
5790dafdce Fixed constraint in VCU118. 2023-08-02 13:02:28 -05:00
Ross Thompson
c4ae856f92 Clean up vcu118 synth scripts. 2023-08-01 14:39:33 -05:00
Ross Thompson
06efd2cdde Pushed performance of arty a7 to 23Mhz. 2023-07-31 14:13:09 -05:00
Jacob Pease
9d33e08dbb Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
b626f2185a Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
Ross Thompson
b1f7a5768f Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
Ross Thompson
49b87d4550 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
065e5e98c9 Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
Ross Thompson
63afd95ad3 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
ab6ef5bb58 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
2752e5de4c Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
97a16f75dc Fixed typo in fpga top for arty a7. 2023-07-19 11:37:29 -05:00
Ross Thompson
e4d6a9f8c6 Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
6a2b752fc0 Updated arty a7 fpga top. 2023-07-17 15:55:57 -05:00
Jacob Pease
b3aaa87cba Modified bootloader to access GUID partitions. SDC interrupt to PLIC. 
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.

The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself  was modified to accept the
SDC interrupt signal.
 2023-07-14 13:36:44 -05:00
Ross Thompson
7aecd72c35 Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. 2023-06-22 12:55:49 -05:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
af187d96ca Updated fpga wave config. 2023-06-19 12:28:30 -05:00
Ross Thompson
1a23f1360f Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
0423d7df82 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
443c568994 Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
c44d4321fb FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
Jacob Pease
40f81d5da6 The Vivado-RISC-V SDC works. Wally is now booting through it. 2023-05-26 15:42:33 -05:00
Ross Thompson
6907f0ccc1 FPGA makefile update. 2023-04-25 16:24:26 -05:00
Ross Thompson
f22e6d0e48 Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 11:08:35 -05:00
Ross Thompson
b13fe870cf Yeah We boot linux on the arty a7! 2023-04-19 11:17:33 -05:00
Ross Thompson
1fec535b32 Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram. 
but the data is wrong.
 2023-04-19 10:35:18 -05:00
Ross Thompson
224bf74530 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Ross Thompson
367bd0f8dc More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
668e69fdc9 Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Jacob Pease
2839f4f41a AHB triggers write, but AXI side doesn't update. 2023-04-18 15:23:22 -05:00
Ross Thompson
3588c53e66 It's almost working. 2023-04-18 14:24:59 -05:00
Ross Thompson
deb0bfc24d Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
777bec2e24 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00
Ross Thompson
b2b30936be Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
fbbba0e5c2 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
2cbaa5c27b Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Ross Thompson
480562e53e Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Ross Thompson
b0f0fb1da7 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
Ross Thompson
30d017c258 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
Ross Thompson
fe692dacce Finally got the arty a7 to build. 2023-04-17 11:54:22 -05:00
Ross Thompson
4ad33d7acc OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( 2023-04-17 11:10:19 -05:00
Ross Thompson
5591b447d6 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Ross Thompson
f4734c0d1b Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Ross Thompson
2f8359e6cc Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
d967e05c20 Finally fixed the ddr3 mig script to work correclty. 2023-04-14 11:41:51 -05:00
Ross Thompson
777edb0fcd Progress on arty a7 board. 2023-04-13 17:57:12 -05:00
Ross Thompson
4563b650bf Fixed more bugs in the ila debug constraints. 2023-04-11 14:32:53 -05:00
Ross Thompson
e490ab09cf Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
6c07a2e595 Fixed sum bugs with arty a7 ila script. 2023-04-11 10:00:06 -05:00
Ross Thompson
c4e5b8db49 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
5bcb0f6ace Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001 Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Ross Thompson
9d9c2b170d Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
Ross Thompson
e7f494ef95 Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
Jacob Pease
b796b1b492 Build doesn't work. AXI Crossbar has problems. 2023-04-06 16:01:58 -05:00
Ross Thompson
6cdfbef2ca Added Jacob's ILA script. 2023-04-06 15:32:36 -05:00
Ross Thompson
1986ef0625 Started constrains file for arty a7 fpga. 2023-03-24 20:38:13 -05:00
Ross Thompson
576d37eb8c Updated fpga constraints to remove critical warning. 2023-03-24 19:09:36 -05:00
Ross Thompson
0afba56927 Updated GPIO signal names to reflect book. 2023-03-24 18:55:43 -05:00
Jacob Pease
2d0199a354 Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore 2023-03-24 17:01:27 -05:00
Ross Thompson
be0318209e Updated fpga ila script. 2023-03-06 13:14:48 -06:00
Jacob Pease
449b835fcd Disabled old SD card and attached IOBUF's to new SD peripheral. 2023-02-28 12:20:46 -06:00
Jacob Pease
85d789a7e0 AXI Crossbar is working. Fixed address width in generator script. 2023-02-22 15:13:16 -06:00
Jacob Pease
45b264fa59 Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-02-16 17:36:26 -06:00
Jacob Pease
f2e4274c9c Fixed debug signal names. Builds on the fpga. Bug in the crossbar. 2023-02-16 17:33:21 -06:00
Ross Thompson
ff7dc4f34a fpga constraints updates 2023-02-07 15:22:14 -06:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
Jacob Pease
c36d32f850 Flipped crossbar inputs and outputs to correctly place masters. 2023-01-27 14:57:36 -06:00
Jacob Pease
264f0ba0da Removed IOBUF's from sdc_controller. 2023-01-27 14:35:34 -06:00
Jacob Pease
07e279b5b5 Modified makefile. Added axi protocol converter IP. 2023-01-23 19:30:29 -06:00
Jacob Pease
c8d487b9e6 Created missing wires for axi interfaces in fpgaTop.v. 2023-01-23 19:02:01 -06:00
Jacob Pease
293cc88bd9 Added extra core signal to mark_debug.txt. Modified wally.tcl 2023-01-23 17:00:24 -06:00
Jacob Pease
9b612fbf6c Merge branch 'main' of github.com:openhwgroup/cvw into boot 2023-01-23 12:41:02 -06:00
Ross Thompson
2fc47bab9c More fixes for the debug2.xdc constraints. 2023-01-20 20:48:19 -06:00
Ross Thompson
61efb22db1 More fixes to fpga ila debugger. 2023-01-20 20:28:21 -06:00
Ross Thompson
e28ea2d630 Fixed fpga constraints. 2023-01-20 20:18:04 -06:00
Ross Thompson
0ed9811e31 Updated fpga constraints. 2023-01-20 20:16:33 -06:00
Ross Thompson
4ccea17648 Added license and comments to new script. 2023-01-20 19:50:33 -06:00
Ross Thompson
9c83b2dff5 Updated ignore to exclude copied files. 2023-01-20 19:47:33 -06:00
Ross Thompson
25bd2e4670 Removed mark_debug vivado directive from source code. 
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
 2023-01-20 19:43:18 -06:00
Ross Thompson
6ccb3a0147 Test commit. 2023-01-20 17:27:09 -06:00
Ross Thompson
11c6106022 Repaired fpga debugger. 2023-01-20 15:26:52 -06:00
Ross Thompson
5b740fbf60 Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Jacob Pease
12b379ebd8 Added IOBUFs to SDCDat. Edited debug2.xdc. Dwidth converter error. 2023-01-19 16:57:43 -06:00
Jacob Pease
ee3a9537a8 Fixed errors in uncore and included newsdc stuff in wally.tcl 2023-01-17 16:46:00 -06:00
Jacob Pease
b618518907 Fixed typos. Apparently `defube causes a weird vivado error. 2023-01-13 16:59:18 -06:00
Jacob Pease
dcfb68daee Added IPs to wally.tcl. 2023-01-13 14:36:23 -06:00
Jacob Pease
e5d4277406 Connected the axi_sdc_controller with an axi crossbar. 
Added an adrdec.sv to the adrdecs.sv file for the sake of the
cache. Modified Uncore accordingly.
 2023-01-13 13:56:01 -06:00
Ross Thompson
e0ec45489a Updated constraints to remove DivBusyE. 2022-12-30 10:51:35 -06:00
Ross Thompson
138c3542db Updated fpga constraints. 2022-12-24 10:21:16 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
15042fc856 Updated fpga constraints. 2022-12-21 14:50:01 -06:00
Ross Thompson
13beda7d0c Updated vcu118 piniout. 2022-12-18 14:00:10 -06:00
Ross Thompson
3ee6ed8542 Updated fpga constraints 2022-12-15 16:45:55 -06:00
rachanaerra
10ff69efc1 updated constraints file 2022-12-05 15:05:21 -06:00
Ross Thompson
e99a424ddc Updated top level fpga file. 2022-11-18 11:10:45 -06:00
Ross Thompson
70d7fca750 Updated fpga wave configuration. 2022-11-16 15:57:19 -06:00
Ross Thompson
cf00f85456 Updated vcu118 constraints to run cpu at 38.43Mhz. 2022-11-15 10:19:38 -06:00
Ross Thompson
cc80f1f7b2 Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s). 
Increased CPU clock speed from 30 Mhz to 35 Mhz.
 2022-11-11 15:33:03 -06:00
Ross Thompson
30b2bd263c Updates to fpga constraints. 2022-11-09 13:52:36 -06:00
Ross Thompson
5c49cc4dd0 Fixed bug with fpga makefile. 2022-11-07 09:20:05 -06:00
Jacob Pease
160ca366c8 Added PLIC signals for debugging on FPGA. 2022-10-25 13:57:09 -05:00
Ross Thompson
9ba487c323 Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile. 2022-10-24 15:38:39 -05:00
Ross Thompson
92ace4d8f7 Forget to include updated xdc file. 2022-10-24 13:51:21 -05:00
Ross Thompson
a008c61939 Updated debug2.xdc for interlock fsm changes. 2022-10-19 17:34:47 -05:00
Ross Thompson
92accfb1a6 Updated uart settings and fpga wave config. 2022-10-18 15:05:33 -05:00
Ross Thompson
2d063bbb2d Updated constraints file to work with alternate uart. 2022-10-04 17:35:44 -05:00
Ross Thompson
16e10a4c5b added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
787f5bcccb Fixed fpga debug constraints. 2022-09-03 17:36:29 -05:00
Ross Thompson
53995c2ed3 update to fpga wave. 2022-09-02 15:54:54 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
01a7718471 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
701324eeb8 Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
Ross Thompson
8180d1ade4 Updated fpga debugger to latest RTL version. 2022-08-19 17:13:36 -05:00
Ross Thompson
8b2491c169 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-19 16:39:28 -05:00
Ross Thompson
83bca570ae Modified debugger for updated rtl. 2022-06-04 14:39:55 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
Ross Thompson
db85afcd2d Added more plic debugging signals. 2022-05-21 14:04:08 -05:00
Ross Thompson
6cae5aa88f Updated the fpga constraints. 2022-05-21 13:32:03 -05:00
Ross Thompson
9079e67aae Updated fpga debugger. 2022-05-17 23:04:01 -05:00
Ross Thompson
51add16def Updated debugger constraints. 2022-05-09 10:19:25 -05:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
82356342f0 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
c16dec88de Increased uart baud rate to 230400. 
Added uart signals to debugger.
 2022-04-17 15:23:39 -05:00
Ross Thompson
7d0462dc59 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
43a294dc88 Added signals to ila. 2022-04-07 21:09:50 -05:00
Ross Thompson
9db8471bf2 Added sp to ila. 2022-04-07 16:29:41 -05:00
Ross Thompson
7abde2b566 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
Ross Thompson
64846c800e Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
5ef6cde52e Added more ILA signals. 2022-04-02 16:39:45 -05:00
Ross Thompson
0340c0fd44 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
Ross Thompson
cb945a6a6a Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
4f1258043d Updated constraints file. 2022-03-30 17:48:44 -05:00
Ross Thompson
9f9a273d2c Added bootrom.txt. 2022-03-30 17:29:48 -05:00
Ross Thompson
b3506c755a test. 2022-03-28 17:04:58 -05:00
Ross Thompson
f818b2a428 Updated debug2.xdc ila constraints to match rtl. 2022-03-28 10:52:26 -05:00
Ross Thompson
111e02677d Fixed ila's config. 2022-02-11 13:58:45 -06:00
Ross Thompson
6a82ee0579 Fixed debug2.xdc to match wally changes. 2022-02-08 15:23:44 -06:00
Ross Thompson
b621eb78fb Updated debug2 ila signal names. 2022-01-28 11:43:49 -06:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
db197b6491 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. 2022-01-25 17:48:42 -06:00
Ross Thompson
71eb1df492 Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00
David Harris
ca1f7ce5d3 Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
Ross Thompson
05ebadacad Added PCNextF and PostSpillInstrRawF to ila. 2022-01-19 14:05:14 -06:00
Ross Thompson
305fccfe7a Fixed fpga ila debug to match lsu changes. 2022-01-18 21:13:18 -06:00
Ross Thompson
5cf686429d Merged in the debug ila updates. 2022-01-18 17:29:21 -06:00
David Harris
f7f3882cb8 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
Ross Thompson
26fb09c868 Added additional fsm to ILA. 2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4 Possible fix for the TrapM DTLBMiss suppression. 2022-01-12 14:17:16 -06:00
Ross Thompson
09d605ac6a Updated debug constraints again to match changes in verilog. 2022-01-08 13:28:51 -06:00
Ross Thompson
88d5edaf13 Added advanced Vivado debug scripts. 2022-01-07 17:56:40 -06:00
Ross Thompson
3625fc3bed Patched the ILA's debug2.xdc constraint file to work with the wally memory design. 2022-01-06 15:18:18 -06:00
Ross Thompson
c19b910f6e Updated fpga ILA constraints to match the new changes to the rtl. 2022-01-06 11:56:09 -06:00
Ross Thompson
1ab3a17ff7 Updates to support fpga. 2022-01-05 18:07:23 -06:00
David Harris
115287adc8 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Ross Thompson
53736096a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 10:03:19 -06:00
Ross Thompson
0257c08641 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
79ec4161b6 Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
9f798250ea Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
Ross Thompson
54767822ec Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. 
added icache debugging signals.
 2021-12-15 10:24:29 -06:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
bb79f70a63 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
e6f2a316c8 Missed constraints file for xilinx ILA. 2021-12-12 15:06:29 -06:00
Ross Thompson
51e2b9ea6f Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
Ross Thompson
8bb3d51aad Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3 Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
Ross Thompson
517cae796c Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
41258529f0 Fixed bug in the top level of fpga verilog. 2021-12-03 17:55:36 -06:00
Ross Thompson
cb744280c3 Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Ross Thompson
35dd1b5c9f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
5d4051d1c2 Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
2cfbdb1c47 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
2a7467c76d Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00
Ross Thompson
6a228ade04 Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
Ross Thompson
96926877c4 Created top level FPGA module which replicates the schematic of the initial fpga design. 2021-11-30 17:18:28 -06:00
Ross Thompson
7f52d86980 Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
1117b90f40 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
84116a756e Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
ce91732856 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
Ross Thompson
9a0bf54840 Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00
Ross Thompson
2e0dcaaff9 Fpga simualtion files. 2021-10-11 10:24:40 -05:00