Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.

Browse Source
This commit is contained in:
Ross Thompson 2023-04-17 12:16:31 -05:00
parent fe692dacce
commit 30d017c258
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/generator/xlnx_mmcm.tcl
View File

@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {false} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {15} \
CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName]