Ross Thompson 517cae796c Fixed more constraint issues in fpga. ... Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim.		2021-12-05 15:14:18 -06:00
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constraints	Fixed more constraint issues in fpga.	2021-12-05 15:14:18 -06:00
generator	Fixed more constraint issues in fpga.	2021-12-05 15:14:18 -06:00
sim	Fpga simualtion files.	2021-10-11 10:24:40 -05:00
src	Fixed bug in the top level of fpga verilog.	2021-12-03 17:55:36 -06:00