mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed more issues with arty a7 constarints.
This commit is contained in:
Ross Thompson
parent
f4734c0d1b
commit
5591b447d6
fpga
@ -1,13 +1,13 @@
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# The main clocks are all autogenerated by the Xilinx IP
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# mmcm_clkout1 is the 22Mhz clock from the DDR3 IP used to drive wally and the AHB Bus.
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# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
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# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
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# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
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# clock comes from pin E3 and is 100Mhz
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# output of mmcm is /4 => 25Mhz
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#create_clock -period 25.000 -name mmcm_clkout1 -waveform {0.000 12.500} [get_nets xlnx_ddr3_c0/ui_clk]
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create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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##### clock #####
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set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
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set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
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##### GPI ####
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set_property PACKAGE_PIN D9 [get_ports {GPI[0]}]
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@ -18,8 +18,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 10.000
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##### GPO ####
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@ -28,14 +28,14 @@ set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
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set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
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set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
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set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
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set_max_delay -to [get_ports {GPO[*]}] 10.000
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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@ -47,16 +47,16 @@ set_max_delay -to [get_ports UARTSout] 10.000
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
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set_property DRIVE 4 [get_ports UARTSout]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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#************** reset is inverted
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports reset]
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set_max_delay -from [get_ports reset] 15.000
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set_false_path -from [get_ports reset]
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set_property PACKAGE_PIN C2 [get_ports {reset}]
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@ -104,54 +104,54 @@ set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
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# ddr3
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[2]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[3]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[4]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[5]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[6]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[7]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[8]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[9]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[10]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[11]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[12]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[13]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[14]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[15]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dm[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dm[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[13]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[12]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[11]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[10]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[9]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[8]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[7]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[6]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[5]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[4]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[3]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[2]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[2]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cke[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_odt[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
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set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
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@ -205,6 +205,7 @@ set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
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# **** may have to bring this one back
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#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
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#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 15.000
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set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK]
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@ -28,6 +28,7 @@ FPGA: PreProcessFiles IP SDC
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IP: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/xlnx_ddr3-ArtyA7.log \
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$(dst)/xlnx_mmcm.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log
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@ -13,10 +13,10 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_USED {true} \
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CONFIG.CLKOUT4_USED {false} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {167} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
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CONFIG.CLKIN1_JITTER_PS {50.0} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
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CONFIG.CLKIN1_JITTER_PS {10.0} \
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] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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