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This commit is contained in:
Ross Thompson 2023-04-18 14:24:59 -05:00
parent deb0bfc24d
commit 3588c53e66
3 changed files with 15 additions and 15 deletions
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8
fpga/constraints/constraints-ArtyA7.xdc
View File

@ -18,8 +18,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
set_max_delay -from [get_ports {GPI[*]}] 10.000
##### GPO ####
@ -47,8 +47,8 @@ set_max_delay -to [get_ports UARTSout] 14.000
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
set_property DRIVE 4 [get_ports UARTSout]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout]

10
fpga/generator/xlnx_ddr3-artya7-mig.prj
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@ -42,7 +42,7 @@
</FPGADevice>
<Controller number="0">
<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX-125</MemoryDevice>
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
<TimePeriod>3000</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
@ -114,7 +114,7 @@
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
<Pin IN_TERM="" IOSTANDARD="LVCMOS135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
</PinSelection>
<System_Clock>
@ -126,7 +126,7 @@
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
</System_Control>
<TimingParameters>
<Parameters tcke="5" tfaw="40" tras="35" trcd="13.75" trefi="7.8" trfc="160" trp="13.75" trrd="7.5" trtp="7.5" twtr="7.5"/>
<Parameters tcke="5.625" tfaw="45" tras="36" trcd="13.5" trefi="7.8" trfc="160" trp="13.5" trrd="7.5" trtp="7.5" twtr="7.5"/>
</TimingParameters>
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
@ -135,10 +135,10 @@
<mrDllReset name="DLL Reset">No</mrDllReset>
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/6</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/4</emrRTT>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)">0</emrPosted>
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
<emrDQS name="TDQS enable">Enabled</emrDQS>

12
fpga/src/fpgaTopArtyA7.v
View File

@ -426,12 +426,12 @@ module fpgaTop
.mmcm_locked(mmcm_locked),
// *** What are these?
.app_sr_req(1'b0),
.app_ref_req(1'b0),
.app_zq_req(1'b0),
.app_sr_active(app_sr_active),
.app_ref_ack(app_ref_ack),
.app_zq_ack(app_zq_ack),
.app_sr_req(1'b0), // reserved command
.app_ref_req(1'b0), // refresh command
.app_zq_req(1'b0), // recalibrate command
.app_sr_active(app_sr_active), // reserved response
.app_ref_ack(app_ref_ack), // refresh ack
.app_zq_ack(app_zq_ack), // recalibrate ack
// axi
.s_axi_awid(BUS_axi_awid),