Updated arty a7 fpga top.

2025-02-11 06:05:49 +00:00 · 2023-07-17 15:55:57 -05:00 · 2023-07-17 15:55:57 -05:00 · 6a2b752fc0
commit 6a2b752fc0
parent 42e6364b3d
1 changed files with 1 additions and 1 deletions
--- a/fpga/src/fpgaTopArtyA7.v
+++ b/fpga/src/fpgaTopArtyA7.v
@ -225,7 +225,7 @@ module fpgaTop
     .peripheral_aresetn(peripheral_aresetn));

  // wally
-  wallypipelinedsoc wallypipelinedsoc
+  wallypipelinedsocwrapper wallypipelinedsocwrapper
    (.clk(CPUCLK),
     .reset_ext(bus_struct_reset),
     // bus interface