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Replaced vivado-risc-v addins directory with new SDC repo.

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This commit is contained in:
Jacob Pease 2023-11-16 13:59:12 -06:00
parent 94201e993f
commit ff73f798ed
2 changed files with 5 additions and 9 deletions
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6
.gitmodules vendored
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@ -23,9 +23,9 @@
[submodule "addins/vivado-boards"]
path = addins/vivado-boards
url = https://github.com/Digilent/vivado-boards/
[submodule "addins/vivado-risc-v"]
path = addins/vivado-risc-v
url = https://github.com/eugene-tarassov/vivado-risc-v.git
[submodule "addins/ahbsdc"]
path = addins/ahbsdc
url = https://github.com/JacobPease/ahbsdc.git
[submodule "addins/riscv-arch-test"]
path = addins/riscv-arch-test
url = https://github.com/riscv-non-isa/riscv-arch-test

8
fpga/generator/wally.tcl
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@ -42,13 +42,9 @@ if {$board=="ArtyA7"} {
# read in all other rtl
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
# *** Once the sdc is updated to use ahb changes these to system verilog.
read_verilog [glob -type f ../src/axi_sdc_controller.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc