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Finally got the arty a7 to build.

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This commit is contained in:
Ross Thompson 2023-04-17 11:54:22 -05:00
parent 4ad33d7acc
commit fe692dacce
2 changed files with 3 additions and 3 deletions
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4
fpga/generator/xlnx_ddr3-artya7-mig.prj
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@ -43,10 +43,10 @@
<Controller number="0">
<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX-125</MemoryDevice>
<TimePeriod>6000</TimePeriod>
<TimePeriod>3000</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>102.564</InputClkFreq>
<InputClkFreq>166.666</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>666</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>

2
fpga/generator/xlnx_mmcm.tcl
View File

@ -13,7 +13,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {false} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.6667} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
CONFIG.CLKIN1_JITTER_PS {10.0} \