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Updated ila signals.

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Improve fpga wave config.
added back in the fpga preload.
This commit is contained in:
Ross Thompson 2022-08-25 09:03:29 -05:00
parent e671291c72
commit 701324eeb8
5 changed files with 59 additions and 60 deletions
fpga
constraints
debug2.xdc
generator
wave_config.wcfg
pipelined/src
cache
sram1p1rw.sv
generic/flop
bram1p1rw.sv
uncore
ram.sv

5
fpga/constraints/debug2.xdc
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File diff suppressed because one or more lines are too long

60
fpga/generator/wave_config.wcfg
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@ -10,12 +10,12 @@
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="168fs"></ZoomEndTime>
<ZoomEndTime time="3838fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="452"></NameColumnWidth>
<ValueColumnWidth column_width="141"></ValueColumnWidth>
<ValueColumnWidth column_width="133"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="11" />
<wave_markers>
@ -69,14 +69,6 @@
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/ReadDataM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/ReadDataM[63:0]</obj_property>
<obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
@ -98,14 +90,6 @@
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIP_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9:9]</obj_property>
<obj_property name="ObjectShortName">SIP_REGW[9:9]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group470">
<obj_property name="label">PLIC</obj_property>
@ -148,22 +132,6 @@
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11:0]</obj_property>
<obj_property name="ObjectShortName">MPendingIntsM[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11:0]</obj_property>
<obj_property name="ObjectShortName">SPendingIntsM[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
@ -280,30 +248,6 @@
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9:9]</obj_property>
<obj_property name="ObjectShortName">SIE_REGW[9:9]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1[1:1]</obj_property>
<obj_property name="ObjectShortName">SIE_REGW_1[1:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2[5:5]</obj_property>
<obj_property name="ObjectShortName">SIE_REGW_2[5:5]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group487">
<obj_property name="label">sdc</obj_property>

2
pipelined/src/cache/sram1p1rw.sv vendored
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@ -74,7 +74,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
for(index = 0; index < WIDTH/8; index++)
always_ff @(posedge clk)
if(ce & WriteEnable & ByteMask[index])
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
assign ReadData = StoredData[AdrD];
end

50
pipelined/src/generic/flop/bram1p1rw.sv
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@ -39,6 +39,7 @@ module bram1p1rw
parameter NUM_COL = 8,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
parameter PRELOAD_ENABLED = 0,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
@ -54,6 +55,55 @@ module bram1p1rw
logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
integer i;
if(PRELOAD_ENABLED) begin
initial begin
RAM[0] = 64'h9581819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110060e37;
RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064511;
RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h47858082dfed8b85;
RAM[41] = 64'h40a7853b4015551b;
RAM[42] = 64'h808210a7a02367c9;
end
end
always @ (posedge clk) begin
dout <= RAM[addr];
if(we) begin

2
pipelined/src/uncore/ram.sv
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@ -70,7 +70,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
// single-ported RAM
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
endmodule