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867 Commits

Author SHA1 Message Date
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
c2f2caa3f6 Get non-jump case working 2021-03-14 14:46:21 -04:00
bbracker
b30ea396b8 slightly smarter dtim HREADY 2021-03-13 07:03:33 -05:00
bbracker
63bfd79009 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
12721837f0 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
bbracker
0f49108ee6 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
d4e84c58ed 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
fe4d288589 Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Noah Boorstin
2d1f63b590 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
81b29a3891 More progress 2021-03-09 21:16:07 -05:00
David Harris
bea8ac6d59 WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
David Harris
52d4a04eb0 Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
ca2a65770c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
bbracker
612f7a9ee4 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
a1223ee13b more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
2cd0f19129 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
62dd9e3075 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Thomas Fleming
97e9baa316 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
85dcbee86b Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
0af002eb2f busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Ross Thompson
a982ad7a9a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
5374dca1b9 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a fixed various bugs 2021-03-04 22:18:19 +00:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Thomas Fleming
38bd683f2d Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
5c456e2d7f busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Shreya Sanghai
f95a1eadd9 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
7cd8f1a592 added performance counters 2021-03-04 11:42:52 -05:00
Ross Thompson
d0223da2f7 Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120 Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24 Fix to 32-bit option of commit 2d40898158 2021-03-04 01:33:34 -06:00
Thomas Fleming
d821a1dbfa Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956 Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Thomas Fleming
692d4152fa Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Noah Boorstin
923489fe16 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
b3247eadd2 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
f11b3108d8 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
David Harris
23a1cf63b3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
6f4e8b723e Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
2d40898158 Properly implemented the fix from commit 5fee65231e 2021-02-28 22:22:04 -06:00
Noah Boorstin
a267115635 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
17715085ba busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
856a1079cc busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
Noah Boorstin
2769b147cb busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489 busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
0596d61a2a busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
e8b306bcba merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
1b61d78ac2 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
David Harris
bad180fc15 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
f57096a5d2 Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
b0a5052bcf FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
a35fdac75b Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
5fee65231e Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Katherine Parry
07641203ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
906ec30339 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
c42c485377 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
7737b0f709 Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
f372e2b8e8 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
e146946e58 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
c856003f73 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
597dd1e7e6 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
7d6093b302 Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Thomas Fleming
ca51e7ca1c Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
87ad559a90 Updated creation date of mul 2021-02-18 08:13:08 -05:00
Ross Thompson
bbe0db3ebe Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
fe7299c155 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
492ec0ee78 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00
David Harris
e8d3c7d9e7 Multiplier tweaks 2021-02-17 16:00:27 -05:00
David Harris
e64e8afb7f Started to integrate OSU divider 2021-02-17 15:38:44 -05:00
David Harris
a7dd20b388 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
43f9abdbed busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
adc5d5bc1a Added MUL 2021-02-15 22:27:35 -05:00
Ross Thompson
ca546beaf8 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 
This is not yet tested but the system verilog does compile.
 2021-02-15 14:51:39 -06:00
David Harris
cc42655789 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Ross Thompson
935e9e59e9 added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. 2021-02-14 15:13:55 -06:00
Ross Thompson
8486f426b7 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. 2021-02-14 11:06:31 -06:00
bbracker
deb7780897 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
David Harris
b121b90b28 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
842c374de9 Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
74bc4c0444 Fixed lw by delaying read value by one cycle 2021-02-07 23:28:21 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00
Noah Boorstin
c03f69fb80 Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Brett Mathis
11e2666bb2 Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
David Harris
2a80bcf543 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 19:44:43 -05:00
David Harris
756352f129 Minor tweaks 2021-02-02 19:44:37 -05:00
Noah Boorstin
b5f474d9f5 same thing but do that right this time 2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55 change undefined syntax in extend.sv 
don't need verilator execption anymore
 2021-02-02 21:39:20 +00:00
David Harris
429f48e766 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece Changed DTIM latency to 2 cycles 2021-02-02 14:22:12 -05:00
David Harris
616830a3f0 Cleaned up hazard interface 2021-02-02 13:53:13 -05:00
David Harris
229bde5953 Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
bb83fda1d8 Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
David Harris
92bf1674b4 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
Brett Mathis
bcb722272e OSU FPU IP initial commit 2021-02-01 19:33:43 -06:00
David Harris
1a3963bed0 Renamed DCU to DMEM 2021-02-01 18:52:22 -05:00
David Harris
07af481b67 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
29313a108b Working on reading instruction from TIM 2021-01-30 01:57:51 -05:00
David Harris
5429424871 Adding stalls for memory delays 2021-01-30 01:43:49 -05:00
David Harris
26c560fba3 Added HCLK and HRESETn 2021-01-30 00:56:12 -05:00
David Harris
9511dcac84 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
9297376873 Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team 2021-01-29 18:06:36 -05:00
David Harris
6c76962847 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 17:29:01 -05:00
David Harris
9530039e3d Implemented adrdec for uncore 2021-01-29 17:28:53 -05:00
Teo Ene
5e5e03c717 - Removed latch on CSRCReadValM in csrc.sv 
- Changed top level to wallypipelinedhart
 2021-01-29 15:56:51 -06:00
David Harris
d104e5a4be Moving data memory to uncore 2021-01-29 15:37:51 -05:00
David Harris
e4e95bf941 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
David Harris
aedadb7703 Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
David Harris
004cc525e2 Hint to optimize ifu 2021-01-28 21:40:48 -05:00
David Harris
1ad69b52d5 Fixed floating signals in clint and ieu 2021-01-28 15:44:05 -05:00
David Harris
8eebf01dca Fixed c.jr instruction improperly writing ra 2021-01-28 15:18:23 -05:00
David Harris
52d6a01cea Created DCU and moved memdp into DCU 2021-01-28 01:03:12 -05:00
David Harris
af25784b61 Provided PC + 2 or 4 (PCLink) for JAL 2021-01-28 00:22:05 -05:00
David Harris
37a58cea17 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
David Harris
db5f45c240 Moved privileged unit from datapath to hart 2021-01-27 07:46:52 -05:00
David Harris
4318629b32 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
David Harris
b7988e536f Reset Vector moved to config file 2021-01-25 15:57:36 -05:00
David Harris
bf07ec92b5 Added test configurations 2021-01-25 11:28:43 -05:00
Noah Boorstin
1d71282332 small busybear testbench changes 2021-01-24 20:43:47 -05:00
Noah Boorstin
7afa48d4ea Linux testbench works now 
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
 2021-01-24 17:10:00 -05:00
Noah Boorstin
c7e2259af0 Merge branch 'busybear' into main 
Merging busybear testbench into main, keeping main edits of wally src
 2021-01-24 16:28:36 -05:00
Noah Boorstin
6d84658369 sucessfully simulate first 30 instructions 
still need to find a better solution to InstrAccessFault/DataAccessFault though
 2021-01-23 19:01:44 -05:00
Noah Boorstin
71883dca82 More linux testbench fixes 
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(

This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.

Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
 2021-01-23 17:52:05 -05:00
Noah Boorstin
117713be89 Linux test now gets through first 8 instructions! 
fixes the python parser:
  get the value, not function name, of PC
  only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
 2021-01-23 16:46:45 -05:00
David Harris
b77ef491fc Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh 2021-01-23 10:48:12 -05:00
David Harris
556e815c4b Cleaned up regfile x0 tied to gnd 2021-01-23 10:22:20 -05:00
David Harris
c6c5dcb2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-23 10:19:28 -05:00
David Harris
b28129fcc3 Initial checkin of UART 2021-01-23 10:19:09 -05:00
Noah Boorstin
a66bd9008c slightly more info on errors, add instruction decoding 2021-01-22 21:14:45 -05:00
Noah Boorstin
cdcacb8dbe change how testbench reads data 
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
 2021-01-22 20:27:01 -05:00
Noah Boorstin
379fc6d5ca change regfile to not hold state of x0 2021-01-22 15:12:33 -05:00
Noah Boorstin
adfeb29b77 change regfile to not hold state of x0 2021-01-22 15:11:55 -05:00
Noah Boorstin
5b0070ac0b Start adding register checking 
I'm now realizing we need to simulate loads, or else these will all be wrong
 2021-01-22 15:11:13 -05:00
Noah Boorstin
6d88c57f0f load instructions from file line by line 2021-01-22 14:11:17 -05:00
Noah Boorstin
3f2820646d More testbench setup work 
- Copy bare-bones testbench from E85
   - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
 - Create .gitignore for vsim files
 - Make PC reset a macro, change to 0x1000 to conform to the bootloader

I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo

for now it lives in /mnt/scratch/riscv_testbench/
 2021-01-21 17:55:05 -05:00
Noah Boorstin
b93a37cdb6 copy testbench to modify for busybear 2021-01-21 16:17:34 -05:00
David Harris
2f24249d17 testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 2021-01-20 01:04:28 -05:00
David Harris
f9ad54f18c Changed to . notation for instantiation, cleaned up dmem 2021-01-18 20:16:53 -05:00
David Harris
cf0958c54e Added GPIO 2021-01-15 00:25:56 -05:00
David Harris
cccb47d795 Added GPIO 2021-01-15 00:19:31 -05:00
David Harris
d6a6f67b04 Initial Checkin 2021-01-14 23:37:51 -05:00