Noah Boorstin a66bd9008c slightly more info on errors, add instruction decoding		2021-01-22 21:14:45 -05:00
..
alu.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
clint.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
controller.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
csr.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
csrc.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
csri.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
csrm.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
csrn.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
csrs.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
csrsr.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
csru.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
datapath.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
dmem.sv	testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64	2021-01-20 01:04:28 -05:00
dtim.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
extend.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
flop.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
gpio.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
hazard.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
imem.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
instrDecompress.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
memdp.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
mux.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
pclogic.sv	More testbench setup work	2021-01-21 17:55:05 -05:00
privileged.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
privilegeDecoder.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
privilegeModeReg.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
regfile.sv	change regfile to not hold state of x0	2021-01-22 15:11:55 -05:00
shifter.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
testbench-busybear.sv	slightly more info on errors, add instruction decoding	2021-01-22 21:14:45 -05:00
testbench.sv	testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64	2021-01-20 01:04:28 -05:00
trap.sv	Initial Checkin	2021-01-14 23:37:51 -05:00
wally-macros.sv	More testbench setup work	2021-01-21 17:55:05 -05:00
wallypipelined.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00
wallypipelinedhart.sv	Changed to . notation for instantiation, cleaned up dmem	2021-01-18 20:16:53 -05:00