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582 Commits

Author SHA1 Message Date
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
bbracker
efb5d1dbc0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-04 00:06:27 +00:00
bbracker
443dd40ea8 remove imperas32p tests 2022-03-04 00:06:18 +00:00
David Harris
545f569f78 Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas 2022-03-03 15:38:08 +00:00
David Harris
080fef6436 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 23:47:16 +00:00
David Harris
8fbdbba81a fma file fixes 2022-03-02 23:47:01 +00:00
bbracker
e28ca531e0 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
be2f668867 but apparently QEMU doesn't show UXL in SSTATUS 2022-03-02 22:44:19 +00:00
bbracker
01e0f2f0d2 update SXL UXL bits in MSTATUS to match new QEMU trace 2022-03-02 22:15:57 +00:00
bbracker
c1290d493f add CSRs to waveview 2022-03-02 18:31:10 +00:00
bbracker
d7b8c9d877 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
6c422cd357 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-02 17:46:40 +00:00
David Harris
3bea7bb431 removed imperas-riscv-tests 2022-03-02 17:28:20 +00:00
bbracker
5f5cc514b8 fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
4f22a55dd4 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
David Harris
1661983345 FMA project ready to start 2022-03-01 20:58:08 +00:00
bbracker
41b3912abc buildroot graphical sim bugfix 2022-03-01 03:24:23 +00:00
bbracker
04ace8c154 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
d620fb4442 deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
David Harris
f314e60dc8 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
f0a7ae2bba adrdecs comments 2022-02-28 20:33:41 +00:00
David Harris
e108eb5195 Modified address decoder for native access to CLINT 2022-02-28 19:13:14 +00:00
David Harris
3519a20ccf hptw cleanup for synthesis 2022-02-28 05:54:34 +00:00
David Harris
bb14dba9be Created softfloat_demo showcasing how to do math with SoftFloat 2022-02-27 18:17:21 +00:00
David Harris
046259cff8 Moved regression work directories to regression/wkdir to reduce clutter 2022-02-27 17:35:09 +00:00
David Harris
c7b5d32a72 Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior 2022-02-27 17:23:33 +00:00
David Harris
c6561d1e8b Moved FMA back into source tree to facilitate synthesis 2022-02-27 15:41:41 +00:00
David Harris
eb0bbacd43 Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue 2022-02-27 15:12:10 +00:00
David Harris
274ecf13ad Moved fma directory 2022-02-27 14:20:15 +00:00
David Harris
5a5142c14f fma simulation infrastructure 2022-02-27 04:36:43 +00:00
David Harris
d917cc1379 fma passing multiply vectors 2022-02-27 04:36:01 +00:00
David Harris
8a55935456 simplified fma Makefile 2022-02-26 19:55:42 +00:00
David Harris
1852eccaab Made softfloat.a a symlink 2022-02-26 19:53:04 +00:00
David Harris
87d1a8a1ac Added start of fma 2022-02-26 19:51:19 +00:00
David Harris
eda60a7691 Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
Ross Thompson
97d64201f7 Fixed bug with DAPageFault being wrong when HPTW writes not supported. 2022-02-23 10:54:34 -06:00
Ross Thompson
53f13d4cbc More spillsupport more structual. 2022-02-23 10:27:14 -06:00
Ross Thompson
c23f6c7d90 Fixed bug with spill support and Instruction DA Page Faults. 2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287 Added generates to pcnextf muxes for privileged and caches. 2022-02-22 22:45:00 -06:00
Ross Thompson
d331b9f29d Fixed "bug" with wally-pipelined.do 2022-02-22 22:19:25 -06:00
Ross Thompson
6a52f95cc8 Minor busdp cleanup. 2022-02-22 17:28:26 -06:00
Ross Thompson
59a2c09c5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-22 14:45:53 -06:00
Ross Thompson
90be3d4360 Clarified interlockfsm. 2022-02-22 11:31:28 -06:00
bbracker
b8fd06576c fix lint bugs in PLIC and UART 2022-02-22 05:04:18 +00:00
bbracker
a6047697c3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
6caa97bb26 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
bbracker
e7934c585a change RX side of UART to aslo be LSB-first 2022-02-22 03:34:08 +00:00
Ross Thompson
3a29504279 Added some clearity to lsuvirtmem.sv. 2022-02-21 17:20:58 -06:00
Ross Thompson
ca59778c5a Annotated IFU for mux changes. 2022-02-21 17:20:34 -06:00
Ross Thompson
2f711fb642 Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW. 2022-02-21 16:54:38 -06:00
Ross Thompson
0c65ea96d8 Cleaned up names in lsuvirtmem. 2022-02-21 16:44:30 -06:00
Ross Thompson
a6e83a2ca2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 12:46:22 -06:00
Ross Thompson
56fc6d0d7c Minor cleanup of lsu. 2022-02-21 12:46:06 -06:00
ushakya22
67780305ae Moved order of reading a, b, and result from test vectors file so that result 
matches up with inputs a and b
 2022-02-21 17:28:11 +00:00
ushakya22
88060a74f5 - created new testbench file instead of having it at the bottom of the srt file 
- uses unpacker to parse 64 bit floating point numbers
- updated testbench to read from new testvectors generated by exptestbench

Notes:
MEM_WIDTH updated to be 64*3
Input numbers and output result is 64 bit number
MEM_SIZE set to 60000
 2022-02-21 16:24:50 +00:00
ushakya22
d1089163a9 - Created exponent divsion module 
- top module includes exponent module now

Notes:
- may be a better implementation of the exponent module rather than
having what I believe are two adders currently
 2022-02-21 16:13:30 +00:00
ushakya22
c6bd51a707 Changed Makefile to compile exptestgen instead of testgen 2022-02-21 16:08:45 +00:00
ushakya22
08d997d68b reverted srt_standford back to original file pre modifications by Udeema 2022-02-21 16:08:09 +00:00
ushakya22
1495f6ac70 verilator lint for srt 2022-02-21 16:05:43 +00:00
ushakya22
5b83ad0929 Created test vector generation file for exponent and mantissa division 2022-02-21 16:04:41 +00:00
Ross Thompson
f48b12b089 Moved mux into lsuvirtmem. 2022-02-21 09:31:29 -06:00
Ross Thompson
cbf4395457 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-21 09:06:09 -06:00
Kip Macsai-Goren
d1578d8356 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
5bdb612567 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-21 00:34:54 +00:00
Ross Thompson
ae06785b9f Minor changes to LSU. 2022-02-19 14:38:17 -06:00
David Harris
20a5798f43 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-18 23:08:47 +00:00
David Harris
6a0ffff05d Removed problematic warning about reaching default state in HPTW 2022-02-18 23:08:40 +00:00
Kip Macsai-Goren
4113d64b19 added 32 bit pma tests to regression even though they've been working fo a while 2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
c3523dfa15 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Ross Thompson
6cd9d84e7f New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
ad237b3ce5 Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
Ross Thompson
cbac34943c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-17 14:49:37 -06:00
Ross Thompson
0eec096474 Rough implementation passing regression test with hptw atomic writes to memory. 2022-02-17 14:46:11 -06:00
David Harris
f3c7025ade Started make allsynth to try many experiments 2022-02-17 17:57:02 +00:00
Ross Thompson
2fc7dc3e57 Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB. 2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622 Broken state. address translation not working after changes to hptw to support atomic updates to PT. 2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc Added additional suppresses to vsim command incase buildroot files are missing. 2022-02-16 17:05:54 -06:00
Ross Thompson
c9e33208e3 Moved a few muxes around after sww changes. 2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b cleanup of signal names. 2022-02-16 15:29:08 -06:00
Ross Thompson
6dc12b4968 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 15:22:35 -06:00
Ross Thompson
27042f028e Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path. 2022-02-16 15:22:19 -06:00
David Harris
c23db6a31e Cleaned warning on HPTW default state 2022-02-16 17:40:13 +00:00
David Harris
01fa5c94bd Register file comments about reset 2022-02-16 17:21:05 +00:00
Ross Thompson
c56c4db47f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-16 09:48:16 -06:00
Skylar Litz
0c69d3291d update bugfinder script to new file organization 2022-02-15 22:58:18 +00:00
Kip Macsai-Goren
6c1383e2a0 added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
5df0a9531f merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
David Harris
aa990be959 removed csrn and all of its outputs because depricated 2022-02-15 19:59:29 +00:00
David Harris
d8170e9dd3 Mostly removed N_SUPPORTED 2022-02-15 19:50:44 +00:00
David Harris
ed8ac3d881 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
David Harris
5ef8f6bc7e Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
Kip Macsai-Goren
9266bc382e light cleanup for privileged tests 2022-02-15 17:06:16 +00:00
Ross Thompson
fcbb577f31 Cache mods to be consistant with diagrams. 2022-02-14 12:40:51 -06:00
David Harris
143eb0ae65 srt fixes 2022-02-14 18:40:27 +00:00
David Harris
3598e05998 srt batch files 2022-02-14 18:37:46 +00:00
ushakya22
3e2e9bc6a0 bring branch back into main 
Merge branch 'srt_division_with_unpacker' into main
 2022-02-14 18:25:34 +00:00
ushakya22
df561f8550 work in progress exponent handling 2022-02-14 18:24:29 +00:00
David Harris
caa4d83e57 t push 
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
 2022-02-14 01:22:22 +00:00
Ross Thompson
86e117ea77 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-13 18:21:15 -06:00
Ross Thompson
6e1a0af5d0 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
a440bc2ac5 More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd Changed names of signals in cache. 2022-02-13 15:06:18 -06:00
Ross Thompson
f87a6f2c63 More cache cleanup. 2022-02-13 12:38:39 -06:00
ushakya22
a996a5e16c Added unpacker into testbench for srt 2022-02-12 22:05:18 +00:00
David Harris
f5678e25db Synthesis cleanup 2022-02-12 06:25:12 +00:00
David Harris
b537df2651 Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
Ross Thompson
f5c4bca47e Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
6fa9490d0b More cache simplifications. 2022-02-11 22:54:05 -06:00
Ross Thompson
ae2011eb07 Reduced seladr to 1 bit as second bit is same as selflush. 2022-02-11 22:41:36 -06:00
Ross Thompson
cb3d71a63d Reduced complexity of the address selection during flush. 2022-02-11 22:27:27 -06:00
Ross Thompson
a0ee2f3d99 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
b1cba4be2b Updates to linux wave. 2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53 Updated linux wave. 2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468 linux wave cleanup. 2022-02-11 10:48:45 -06:00
Ross Thompson
20456097cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60 Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618 Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
Ross Thompson
9ad4523b9d Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00
Ross Thompson
f23817bf69 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9 Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05 More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7 Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22 Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
327a05c9d8 Added commented out commands to generate saif file from vsim. 2022-02-09 18:40:45 -06:00
Ross Thompson
01126535db Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
d1d014bf1d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
13561c67bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
cecbb3362d rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
3e16730226 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
d5d9bb9d4d Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
David Harris
c07584bb70 rv32e config update 2022-02-08 17:59:50 +00:00
Ross Thompson
c2377eaaf4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 11:36:30 -06:00
Ross Thompson
3cd067ac6a Finished merge. 2022-02-08 11:36:24 -06:00
David Harris
9ad3f26365 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
Ross Thompson
492c1473f3 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
e5097e67d4 Fixed TIM tests; rv32e test still failing 2022-02-08 15:24:37 +00:00
David Harris
e9a519a228 Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail 2022-02-08 12:40:02 +00:00
David Harris
096242a6d8 Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
David Harris
72c2166223 Lab 3 file cleanup 2022-02-08 10:26:37 +00:00
Ross Thompson
190d619940 cachefsm cleanup. 2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1 more partial cleanup of fsm and write enables. 2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875 Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
fcd43ea004 more cleanup. 2022-02-07 13:29:19 -06:00
Ross Thompson
e72d54ea98 More cachefsm cleanup. 2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0 More cachefsm cleanup. 2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571 More cachefsm cleanup. 2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559 More cachefsm cleanup. 2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8 More cachefsm cleanup. 2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473 Cache cleanup. 2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31 More cachfsm cleanup. 2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a Reverted cache change 2022-02-07 14:47:20 +00:00
David Harris
d0c40cca7a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-07 14:43:31 +00:00
David Harris
c21eb67a07 Cache syntax cleanup 2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b More cachefsm cleanup. 2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8 started cachefsm cleanup. 2022-02-06 21:39:38 -06:00
Kip Macsai-Goren
38b75e85a0 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
David Harris
0feb624bab Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
bbracker
27dd363a85 remove sporadic tabs from tests.vh so that it is now only spaces 2022-02-05 23:07:38 +00:00
bbracker
fc2e3d1fbf remove rv32e from regression because it is broken; goes with previous commit 2022-02-05 23:05:21 +00:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
David Harris
0dd8c719ad Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit 2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13 Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
Ross Thompson
1766c0f5ba Removed unused ports from caches and buses. 2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5 Cleanup. 2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533 Moved the hwdata mux back into the busdp. 2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a Merged together the two sub cache line read muxes. 
One mux was used for loads and the other for eviction.
 2022-02-04 22:30:04 -06:00
David Harris
23868a33bc Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537 Moved the sub cache line read logic to lsu/ifu. 2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9 Second optimization of save/restore. 2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6 Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
16b5fee795 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
14c1d86953 rv32e 2022-02-04 01:56:30 +00:00
David Harris
1c049f1f67 renamed configs 2022-02-03 23:36:41 +00:00
David Harris
c3122ce214 sram1rw cleanup 2022-02-03 18:03:22 +00:00
David Harris
0e1d784b60 sram1rw cleanup 2022-02-03 17:50:23 +00:00
David Harris
eb8dd5e7d7 cachereplacementpolicy cleanup 2022-02-03 17:19:14 +00:00
David Harris
5f7326368e cachereplacementpolicy cleanup 2022-02-03 17:18:48 +00:00
David Harris
9b6a4d1d52 cacheway cleanup 2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21 cacheway cleanup 2022-02-03 16:33:01 +00:00
David Harris
0fbc32204c cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
c22f7eb11c cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
e92461159d cache cleanup 2022-02-03 15:36:11 +00:00
Ross Thompson
4a5aa43716 Merge branch 'makefiles' into main 2022-02-03 08:33:50 -06:00
Ross Thompson
55382be055 Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the 
regression directory.  Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
 2022-02-03 08:32:48 -06:00
Ross Thompson
9da3223ce6 Manged to get all the tests compiled and converted to memfiles using new makefiles. 2022-02-03 00:00:15 -06:00
Ross Thompson
41978d59e4 Quick patch to regression-wally to "fix" rv32ic. 2022-02-02 19:24:24 -06:00
Ross Thompson
789cf13be6 broken makefiles. 2022-02-02 19:15:11 -06:00
Ross Thompson
ac19cd48a4 Broken makefiles. 2022-02-02 19:14:42 -06:00
David Harris
9e0055cbb9 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73 changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
172a02551b Removed Busybear and Buildroot Configuration 2022-02-02 20:32:22 +00:00
David Harris
c12407ba6a Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
f3c2e426b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-02 11:41:54 -06:00
Ross Thompson
2f7cf2bc7f Fixed testbench so coremark stops. 2022-02-02 11:37:48 -06:00
David Harris
761dae72fe Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
Ross Thompson
88a408b3e6 Added helpful signals to wavefile. 
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
 2022-02-02 10:15:54 -06:00
Ross Thompson
ae36931bb2 Added correct stop condition for coremark. 2022-02-02 09:53:51 -06:00
Ross Thompson
2d8b0aa650 Modified makefiles to generate function address to name mappings for modelsim. 2022-02-01 18:25:03 -06:00
Ross Thompson
058b368a22 Improved function_radix to not printout warnings when no valid function is found. 2022-02-01 18:03:09 -06:00
Ross Thompson
138b17a399 Setup the main regression test to be able to handle coremark. 2022-02-01 17:00:11 -06:00
Ross Thompson
910d16b642 More cleanup of IFU. 2022-02-01 14:32:27 -06:00
Ross Thompson
a9b4f9b1e7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-01 10:50:38 -06:00
Ross Thompson
99bb281944 Updated fpga's bootloader to reflect the changes to the gpio address change. 2022-02-01 10:43:24 -06:00
Ross Thompson
dce9ee12b4 IFU and LSU now share the same busdp module. 2022-01-31 16:25:41 -06:00
Ross Thompson
a04aa283cb partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
b05abc1795 cleanup. 2022-01-31 13:29:04 -06:00
Ross Thompson
c1311ca56a Fixed modelsim warning with linux simulation. 2022-01-31 12:57:02 -06:00
Ross Thompson
d2ab17e1af Repaired linux-wave.do 2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5 Repaired wavefile and fixed modelsim warning. 2022-01-31 12:34:17 -06:00
Ross Thompson
1476a79ea2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
fa8914a830 Cleanup busdp. 2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4 Moved lsu virtual memory logic into separate module. 2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2 Removed unused signals in the LSU. 2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184 Moved atomic logic to own module. 2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183 Encapsulated the bus data path into a separate module. 2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
1077cf08b0 added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
David Harris
2d112698b7 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
Ross Thompson
d52c5b0393 LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981 Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878 Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
1c22077841 Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7 Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00