David Harris
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3f2ec0499f
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Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.
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2022-05-03 03:45:41 -07:00 |
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David Harris
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7268ff1fd4
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Changed loop variable in CLINT because of error only seen on VLSI
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2022-05-03 10:10:28 +00:00 |
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Kip Macsai-Goren
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e557e420b6
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added missing SIE test
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2022-04-29 19:54:29 +00:00 |
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Kip Macsai-Goren
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5df381e26f
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renamed PIE-stack tests to status-mie for clarity
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2022-04-29 18:30:39 +00:00 |
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Kip Macsai-Goren
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c3ffcd0e95
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removed old unused tests from wally arch tests
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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3d1e1202f3
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set WFI timeout to after 16 bits of counting for all configs
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2022-04-28 18:14:08 +00:00 |
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Kip Macsai-Goren
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0e5cc40360
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added 32 bit versions of new tests. all but timeout wait pass regression
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2022-04-28 18:14:07 +00:00 |
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Skylar Litz
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970f6c4222
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-27 10:50:19 -07:00 |
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Skylar Litz
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594db170de
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fix AttemptedInstructionCount from ground zero
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2022-04-27 10:45:40 -07:00 |
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David Harris
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6e8b27de17
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Added torture.tv test vectors
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2022-04-27 13:08:36 +00:00 |
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David Harris
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ffd4713fd1
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Checked in torture.tv
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2022-04-27 13:06:24 +00:00 |
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David Harris
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9042844b38
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Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv
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2022-04-26 19:41:30 +00:00 |
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Kip Macsai-Goren
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89cce88d33
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fixed incorrect configs in regression
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2022-04-25 19:28:47 +00:00 |
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Kip Macsai-Goren
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0f4ca62157
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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Kip Macsai-Goren
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8ad920fcb3
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fixed initial value, timing on fs bits changing after floating point instruction
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2022-04-25 19:17:29 +00:00 |
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Kip Macsai-Goren
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da29193f9b
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removed atomic, floating point from privileged tests configs
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2022-04-25 19:13:15 +00:00 |
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Kip Macsai-Goren
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7ff85258f0
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added new tests to tests.vh, comented out until they pass regression
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2022-04-25 18:22:44 +00:00 |
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Kip Macsai-Goren
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7fe33b2147
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Lowered WFI timeout wait time for privileged configs
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2022-04-25 17:47:10 +00:00 |
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David Harris
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cf1fde62fb
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Restored MPRV behavior per spec
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2022-04-25 14:52:18 +00:00 |
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David Harris
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0ede295e88
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Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
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2022-04-25 14:49:00 +00:00 |
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David Harris
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851d5e8c5e
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Added MTINST hardwired to 0, and added timeout of U-mode WFI
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2022-04-24 20:00:02 +00:00 |
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David Harris
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16ad1e0cab
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Fixed InstrMisalignedFaultM mtval
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2022-04-24 17:31:30 +00:00 |
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David Harris
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f1ddbb169c
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Improved priority order and mtval of traps to match spec
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2022-04-24 17:24:45 +00:00 |
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David Harris
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03f84bf11c
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Extended sim time to fully boot Linux. Added comments to hazard unit
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2022-04-24 13:51:00 +00:00 |
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Kip Macsai-Goren
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7bc6943527
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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bbracker
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5e76c83309
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deprecate unused LINUX_FIX_READ macro
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2022-04-21 19:14:47 -07:00 |
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bbracker
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afc38abe08
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change how tristate I/O is spoofed in GPIO loopback test
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2022-04-21 10:31:16 -07:00 |
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Ross Thompson
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8fcd4d47b7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Ross Thompson
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165a36acac
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Modified wally-pipelined.do for no trace linux sim.
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2022-04-21 09:52:33 -05:00 |
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David Harris
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5c607f2b6b
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Simplified profile for UART boot; added warnings on UART Rx errors
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2022-04-21 04:54:45 +00:00 |
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Kip Macsai-Goren
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cd53163d9a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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080963c381
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fixed rv32ia to support clint and GPIO for priv tests
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2022-04-20 17:31:34 +00:00 |
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Kip Macsai-Goren
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510021af65
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Ross Thompson
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546ef08eb2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-19 14:09:50 -05:00 |
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David Harris
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1f7a95637a
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Added baby torture tests
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2022-04-19 15:13:06 +00:00 |
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David Harris
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a8ad7be246
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Fixed WFI decoding in IFU
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2022-04-18 19:02:08 +00:00 |
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Kip Macsai-Goren
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1ba328324b
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Added GPIO loopback to let outputs cause interrupts
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2022-04-18 07:22:49 +00:00 |
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Kip Macsai-Goren
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64698aa806
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Shreya Sanghai
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fd3920b217
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replaced k with bpred size
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2022-04-18 04:21:03 +00:00 |
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Shreya Sanghai
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c3164f0ce1
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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462158ea92
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LSU name cleanup
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2022-04-18 03:18:38 +00:00 |
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Ross Thompson
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a99466a487
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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David Harris
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4a7effaf9e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-04-18 01:30:11 +00:00 |
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David Harris
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2882460c94
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Renamed FinalAMOWriteDataM to AMOWriteDataM
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2022-04-18 01:30:03 +00:00 |
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David Harris
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861fbd698b
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Run 4M instructions in buildroot test to get through kernel & VirtMem startup
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2022-04-18 01:29:38 +00:00 |
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Ross Thompson
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c045e3afd8
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Added back the instret counter to ILA.
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2022-04-17 18:44:07 -05:00 |
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Ross Thompson
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c409bde6ae
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fixed no forcing bug in linux testbench.
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2022-04-17 17:49:51 -05:00 |
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David Harris
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2819a1c305
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Remvoed bytemask anding from FinalWriteDataM in subwordwrite
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2022-04-17 22:33:25 +00:00 |
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David Harris
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812b56acc6
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Prefix comparator cleanup
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2022-04-17 21:53:11 +00:00 |
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David Harris
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de5b61291f
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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