Jordan Carlin
|
783b81f8b8
|
VCD support in all simulators
|
2024-12-02 13:52:44 -08:00 |
|
Jordan Carlin
|
68205b844d
|
Update Breker platform.yaml and test compilation
|
2024-12-02 13:21:55 -08:00 |
|
Jordan Carlin
|
311125f4bd
|
WIP Breker
|
2024-12-02 13:11:55 -08:00 |
|
Jordan Carlin
|
1932d8bc5d
|
Update testbench makefile to generate memfile even in elf file does not end in .elf
|
2024-12-01 17:56:16 -08:00 |
|
David Harris
|
ec3143f014
|
Updated warning in ramxdetector
|
2024-11-29 12:03:14 -08:00 |
|
David Harris
|
155d1d511b
|
Fixed funct7 code for sinval.vma (issue #1154)
|
2024-11-29 11:39:24 -08:00 |
|
David Harris
|
05189d102a
|
Modifying tracer toward being able to run non-gc configurations in lockstep
|
2024-11-26 22:09:11 -08:00 |
|
David Harris
|
028ffe9f4a
|
Removing obsolete ***
|
2024-11-20 07:23:51 -08:00 |
|
David Harris
|
ce7b036b78
|
Merge pull request #1109 from jordancarlin/lint
More lint cleanup: remove unused params
|
2024-11-16 16:34:15 -08:00 |
|
Jordan Carlin
|
00d02e5656
|
fix testbench
|
2024-11-16 12:53:10 -08:00 |
|
Jordan Carlin
|
2b57633217
|
Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench
|
2024-11-15 22:52:21 -08:00 |
|
Rose Thompson
|
fcf4ca1417
|
Disabled tracer print.
|
2024-11-15 08:32:43 -06:00 |
|
Rose Thompson
|
3596be433c
|
Fixed the tracer so that traps don't clear the instruction or PC bits.
|
2024-11-15 08:31:19 -06:00 |
|
David Harris
|
c02a649c3b
|
Fixed warnings related to tracer variables
|
2024-11-15 05:33:16 -08:00 |
|
Huda-10xe
|
b2789f304a
|
Removing old code (not in use anymore)
|
2024-11-15 00:39:16 -08:00 |
|
Jordan Carlin
|
9d2a5c6e03
|
Fix wallyTracer bug
|
2024-11-14 15:31:10 -08:00 |
|
Jordan Carlin
|
51d7eea98a
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi32
|
2024-11-14 15:04:11 -08:00 |
|
Jordan Carlin
|
61c5d035e9
|
Add mseccfg shell to wallyTracer and reformat CSRs
|
2024-11-14 15:03:13 -08:00 |
|
Rose Thompson
|
5e4f4c2072
|
Simple change to ensure Trapped instructions are included with rvvi as
valid instructions. Required for functional coverage.
|
2024-11-14 16:14:02 -06:00 |
|
Jordan Carlin
|
14e9a39523
|
pmps working for RVVI in RV32
|
2024-11-13 22:12:11 -08:00 |
|
Jordan Carlin
|
d666a0dd7b
|
Update formatting in an attempt to understand what's happening in this file
|
2024-11-13 18:26:53 -08:00 |
|
Jordan Carlin
|
017b3e9872
|
Fix 32 bit CSRs in wallyTracer
|
2024-11-13 17:01:01 -08:00 |
|
Rose Thompson
|
77d47e531f
|
Merge branch 'main' into lrufixes
|
2024-11-13 10:34:21 -06:00 |
|
Rose Thompson
|
2fe73f8174
|
Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
|
2024-11-13 00:02:51 -06:00 |
|
Rose Thompson
|
8993432928
|
Resolved issue with questa not liking the TEST +arg as a generate.
|
2024-11-12 23:57:30 -06:00 |
|
Rose Thompson
|
ef7072b7c2
|
Merge branch 'main' into lrufixes
|
2024-11-12 17:57:28 -06:00 |
|
Rose Thompson
|
8659d6efdb
|
Resolved all CacheSim.py vs Wally mismaches.
|
2024-11-12 17:24:06 -06:00 |
|
Rose Thompson
|
57fbd35484
|
Fixed lint errors in loggers.sv with Kaitlin.
|
2024-11-12 15:03:30 -06:00 |
|
Rose Thompson
|
b7b7c79726
|
CBO.FLUSH was not clearing the valid bit if the cacheline was clean.
|
2024-11-12 14:16:55 -06:00 |
|
Rose Thompson
|
5cc1fd4a85
|
Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.
|
2024-11-12 12:08:14 -06:00 |
|
Rose Thompson
|
8a4868ac57
|
Resolved a bug in the cache but there are still mismatches with the cache simulator.
|
2024-11-12 11:35:29 -06:00 |
|
Rose Thompson
|
0cf7b2e45a
|
Progress on fixing the cache simulator to support cbo instructions.
|
2024-11-11 16:37:17 -06:00 |
|
Rose Thompson
|
1629eda608
|
Added btbthrash to tests.vh.
|
2024-10-30 16:07:05 -05:00 |
|
David Harris
|
0555e58afe
|
Removed unnecessary display statement from testbench for DTIM versions
|
2024-10-26 02:12:43 -07:00 |
|
Rose Thompson
|
8fb1673ab3
|
Updated email address authorship for my files.
|
2024-10-15 10:27:53 -05:00 |
|
Rose Thompson
|
2ef7005ea6
|
Fixed name of test and added to tests.vh
|
2024-10-13 15:29:27 -05:00 |
|
Huda-10xe
|
b77df83b59
|
Adding DUT signals to the tracer for VM Coverage
|
2024-10-07 03:52:36 -07:00 |
|
Huda-10xe
|
24f97fa696
|
Adding DUT signals to the tracer for VM Coverage
|
2024-10-07 03:49:43 -07:00 |
|
Huda-10xe
|
e0ea37fe21
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi_setup
|
2024-10-07 03:44:43 -07:00 |
|
Huda-10xe
|
0817c69152
|
Adding priv coverage to ISACOV
|
2024-10-07 03:44:35 -07:00 |
|
Rose Thompson
|
9139f91c56
|
Updated tests.vh to include floatmisc into coverage64gc. And removed
all tests from custom suite. These should be run individually.
|
2024-10-02 17:21:22 -05:00 |
|
Rose Thompson
|
083e583877
|
Added extra $display to print the test name during coverage.
|
2024-10-02 15:41:14 -05:00 |
|
Rose Thompson
|
6ad27a436c
|
Updated coverage64gc test suite to include new tlb, hptw, and amo
fault tests.
|
2024-10-02 15:29:50 -05:00 |
|
Jordan Carlin
|
23f037e76e
|
Add misaligned cjal and cjalr tests
|
2024-09-29 22:33:11 -07:00 |
|
Jordan Carlin
|
8a58f9556e
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into arch-test-update
|
2024-09-29 17:16:05 -07:00 |
|
Jordan Carlin
|
766b0a83d7
|
Remove wally32d tests since they are covered elsewhere now
|
2024-09-29 10:27:20 -07:00 |
|
Jordan Carlin
|
330eda243c
|
Remove wally32i and wally64i tests since they are covered elsewhere now
|
2024-09-29 10:26:08 -07:00 |
|
Jordan Carlin
|
8a0ca9826a
|
Remove wallycov64i tests
|
2024-09-29 10:24:09 -07:00 |
|
Jordan Carlin
|
ef442808a9
|
Remove old imperas tests
|
2024-09-29 10:18:04 -07:00 |
|
Jordan Carlin
|
2f09369921
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into arch-test-update
|
2024-09-29 01:51:22 -07:00 |
|
Jordan Carlin
|
716bee3d26
|
Restore testbench_fp to load from vectors directory
|
2024-09-29 00:57:41 -07:00 |
|
Jordan Carlin
|
cc484c117d
|
Update tests.vh formatting and whitespace
|
2024-09-26 15:49:29 -07:00 |
|
Jordan Carlin
|
788bc6d0b0
|
Update D fma_b15 tests based on new riscv-arch-test structure
|
2024-09-24 14:02:30 -07:00 |
|
Rose Thompson
|
1345a0f315
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2024-09-24 10:13:50 -05:00 |
|
Jordan Carlin
|
4081d4de58
|
Replace tabs with spaces in testbench_fp
|
2024-09-22 21:33:08 -07:00 |
|
Jordan Carlin
|
5618e27424
|
fix testbench_fp formatting
|
2024-09-22 20:40:20 -07:00 |
|
Jordan Carlin
|
5abe709dcb
|
Load fp vectors from ieee or riscv subdirectory
|
2024-09-16 14:49:52 -07:00 |
|
David Harris
|
5af07db76c
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-08-31 16:20:05 -07:00 |
|
Jordan Carlin
|
80750f2308
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
|
2024-08-29 15:55:54 -07:00 |
|
David Harris
|
6157023d16
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2024-08-29 15:07:18 -07:00 |
|
David Harris
|
0e9e7d0a49
|
Fixed wallyTracer floating-point register FLEN
|
2024-08-29 11:11:19 -07:00 |
|
Rose Thompson
|
6ad2c2e7a6
|
Merge pull request #935 from davidharrishmc/dev
Added lockstep support for RV32. Not all wally privileged tests pass…
|
2024-08-29 10:45:17 -07:00 |
|
David Harris
|
26f3c2a607
|
Added lockstep support for RV32. Not all wally privileged tests pass yet
|
2024-08-29 10:44:37 -07:00 |
|
Jordan Carlin
|
f0c5d6e4e7
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates
|
2024-08-25 12:14:25 -07:00 |
|
Rose Thompson
|
113d71f1a0
|
More name updates.
|
2024-08-21 10:51:24 -07:00 |
|
Rose Thompson
|
f603d21826
|
Updated my name in multiple locations.
|
2024-08-21 10:50:39 -07:00 |
|
Jordan Carlin
|
413a3fca0e
|
Use $finish for VCS and Verilator in testbench_fp
|
2024-08-11 09:34:29 -07:00 |
|
David Harris
|
be90457250
|
Merge pull request #862 from jordancarlin/verilator_fixes
Remove Verilator hack
|
2024-08-08 20:50:50 -07:00 |
|
David Harris
|
d4a8377406
|
Merge pull request #862 from jordancarlin/verilator_fixes
Remove Verilator hack
|
2024-08-08 20:50:50 -07:00 |
|
David Harris
|
77c2a86cef
|
Merge pull request #869 from jordancarlin/installation
Installation and setup overhaul
|
2024-08-08 15:39:23 -07:00 |
|
David Harris
|
bc70f0b933
|
Merge pull request #869 from jordancarlin/installation
Installation and setup overhaul
|
2024-08-08 15:39:23 -07:00 |
|
David Harris
|
010038ec32
|
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
|
2024-08-08 05:27:35 -07:00 |
|
David Harris
|
fa98ae8c30
|
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
|
2024-08-08 05:27:35 -07:00 |
|
Jordan Carlin
|
357175f1c8
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
|
2024-08-07 20:22:55 -07:00 |
|
Jordan Carlin
|
76eef03fe4
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
|
2024-08-07 20:22:55 -07:00 |
|
Huda-10xe
|
2405b6c1e2
|
Adding RVVI Functional Coverage Support
|
2024-08-07 14:31:16 +05:00 |
|
Huda-10xe
|
0303314f4e
|
Adding RVVI Functional Coverage Support
|
2024-08-07 14:31:16 +05:00 |
|
Rose Thompson
|
7164841f83
|
Added padding into the hw rvvi format.
|
2024-08-06 18:34:46 -05:00 |
|
Jacob Pease
|
11ca2567b8
|
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
|
2024-08-06 17:09:39 -05:00 |
|
Jacob Pease
|
af2344d2d5
|
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
|
2024-08-06 17:09:39 -05:00 |
|
Jacob Pease
|
bd07a60c07
|
Updated wally source files for zsbl testing.
|
2024-08-02 15:33:57 -05:00 |
|
Jacob Pease
|
11a057b0b3
|
Updated wally source files for zsbl testing.
|
2024-08-02 15:33:57 -05:00 |
|
Jordan Carlin
|
2f1a101735
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
|
2024-07-25 21:21:57 -07:00 |
|
Jordan Carlin
|
42a9bbf28d
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
|
2024-07-25 21:21:57 -07:00 |
|
Jacob Pease
|
6fc10adc25
|
Added ability to split boot.memfile into boot.mem and data.mem.
|
2024-07-25 11:19:15 -05:00 |
|
Jacob Pease
|
336a413f31
|
Added ability to split boot.memfile into boot.mem and data.mem.
|
2024-07-25 11:19:15 -05:00 |
|
Rose Thompson
|
ce61429bdf
|
Fixed the reset bug in wallyTracer.
|
2024-07-24 13:32:46 -05:00 |
|
Rose Thompson
|
5a6e32576d
|
Fixed the reset bug in wallyTracer.
|
2024-07-24 13:32:46 -05:00 |
|
Rose Thompson
|
d0a5b278b7
|
Factored out the rvvi testbench code into rvvitbwrapper.
|
2024-07-24 13:10:57 -05:00 |
|
Rose Thompson
|
13db14db6b
|
Factored out the rvvi testbench code into rvvitbwrapper.
|
2024-07-24 13:10:57 -05:00 |
|
Rose Thompson
|
b1a711ae0f
|
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
|
2024-07-24 12:47:50 -05:00 |
|
Rose Thompson
|
c11036358a
|
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
|
2024-07-24 12:47:50 -05:00 |
|
Jordan Carlin
|
790f566eaa
|
Remove hardcoded /opt/riscv
|
2024-07-23 23:29:45 -07:00 |
|
Jordan Carlin
|
47452ddaaa
|
Remove hardcoded /opt/riscv
|
2024-07-23 23:29:45 -07:00 |
|
Rose Thompson
|
6c212ebf0e
|
Changes are confirmed to work on the FPGA.
|
2024-07-23 17:39:38 -05:00 |
|
Rose Thompson
|
35efbd6a54
|
Changes are confirmed to work on the FPGA.
|
2024-07-23 17:39:38 -05:00 |
|
Rose Thompson
|
7223b15134
|
Merge branch 'rvvi'
|
2024-07-22 12:01:01 -05:00 |
|
Rose Thompson
|
02f108345a
|
Merge branch 'rvvi'
|
2024-07-22 12:01:01 -05:00 |
|
David Harris
|
f30cc46ec5
|
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
|
2024-07-21 08:26:07 -07:00 |
|
David Harris
|
f5f8a6c50c
|
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
|
2024-07-21 08:26:07 -07:00 |
|