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https://github.com/openhwgroup/cvw
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Fixed lint errors in loggers.sv with Kaitlin.
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@ -46,11 +46,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
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// performance counter logging
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logic BeginSample;
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logic StartSample, EndSample;
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if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
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if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleDelayed, BeginDelayed;
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logic EndSampleFirst, EndSampleDelayed;
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logic EndSampleFirst;
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logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
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string HPMCnames[] = '{"Mcycle",
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@ -89,9 +89,18 @@ module loggers import cvw::*; #(parameter cvw_t P,
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EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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end else begin
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StartSampleFirst = reset;
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EndSample = DCacheFlushStart & ~DCacheFlushDone;
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EndSampleFirst = '0;
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end
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// this code needs to be with embench and coremark but not the else condition
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if (TEST == "embench" | TEST == "coremark") begin
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logic EndSampleDelayed;
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else begin
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assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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end
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/*
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if(TEST == "embench") begin
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// embench runs warmup then runs start_trigger
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@ -132,8 +141,6 @@ module loggers import cvw::*; #(parameter cvw_t P,
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~StartSampleDelayed;
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
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assign BeginSample = StartSampleFirst & ~BeginDelayed;
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