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Remove hardcoded /opt/riscv

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This commit is contained in:
Jordan Carlin 2024-07-23 01:58:19 -07:00
parent 36ffeb2dca
commit 47452ddaaa
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7 changed files with 11 additions and 14 deletions
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4
bin/libppa.pl
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@ -43,7 +43,7 @@ my @cr; my @cf; my @rt; my @ft;
my $libpath; my $libbase; my $cellname; my @corners;
# Sky130
$libpath ="/opt/riscv/cad/lib/sky130_osu_sc_t12/12T_ms/lib";
$libpath ="$ENV{RISCV}/cad/lib/sky130_osu_sc_t12/12T_ms/lib";
$libbase = "sky130_osu_sc_12T_ms_";
$cellname = "sky130_osu_sc_12T_ms__inv_1";
@corners = ("TT_1P8_25C.ccs", "tt_1P80_25C.ccs", "tt_1P62_25C.ccs", "tt_1P89_25C.ccs", "ss_1P60_-40C.ccs", "ss_1P60_100C.ccs", "ss_1P60_150C.ccs", "ff_1P95_-40C.ccs", "ff_1P95_100C.ccs", "ff_1P95_150C.ccs");
@ -53,7 +53,7 @@ foreach my $corner (@corners) {
}
# Sky90
$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
$libpath ="$ENV{RISCV}/cad/lib/sky90/sky90_sc/V1.7.4/lib";
$libbase = "scc9gena_";
$cellname = "scc9gena_inv_1";
@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C");

2
linux/sdcard/Makefile
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@ -1,5 +1,3 @@
RISCV := /opt/riscv
.PHONY: all clean
all:

1
linux/sdcard/flash-sd.sh
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@ -25,7 +25,6 @@ ERRORTEXT="$BOLDRED"ERROR:"$NC"
WARNINGTEXT="$BOLDYELLOW"Warning:"$NC"
# Default values for buildroot and device tree
RISCV=/opt/riscv
BUILDROOT=$RISCV/buildroot
DEVICE_TREE=wally-vcu108.dtb
MNT_DIR=wallyimg

1
linux/sdcard/make-img.sh
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@ -9,7 +9,6 @@ NC='\033[0m'
NAME="$GREEN"${0:2}"$NC"
# File location variables
RISCV=/opt/riscv
IMAGES=$RISCV/buildroot/output/images
FW_JUMP=$IMAGES/fw_jump.bin
LINUX_KERNEL=$IMAGES/Image

6
sim/Makefile
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@ -34,9 +34,9 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
imperasdv_cov:
touch ${SIM}/seed0.txt
echo "0" > ${SIM}/seed0.txt
# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
# ${RISCV}/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
# ${RISCV}/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
# ${RISCV}/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
vcover report -details -html ${SIM}/questa/riscv.ucdb

5
sim/buildrootBugFinder.py
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@ -2,9 +2,10 @@
import sys, os, subprocess
def main():
RISCV = os.environ.get("RISCV")
maxGoodCount = 400e6 # num instrs that execute sucessfully starting from 0
currInstrCount = maxGoodCount
linuxTestvectors = "/opt/riscv/linux-testvectors"
linuxTestvectors = RISCV+"/linux-testvectors"
if not os.path.exists(linuxTestvectors):
sys.stderr.write("Error: Linux testvectors not found at "+linuxTestvectors+"\n")
exit(1)
@ -22,7 +23,7 @@ def main():
break
checkpoint = checkpointList[0]
logFile = logDir+"checkpoint"+str(checkpoint)+".log"
runCommand="{\nvsim -c <<!\ndo wally-batch.do buildroot buildroot /opt/riscv 0 "+str(checkpoint+1)+" "+str(checkpoint)+"\n!\n} | tee "+logFile
runCommand="{\nvsim -c <<!\ndo wally-batch.do buildroot buildroot "+RISCV+" 0 "+str(checkpoint+1)+" "+str(checkpoint)+"\n!\n} | tee "+logFile
print(runCommand)
os.system(runCommand)
try:

6
testbench/testbench.sv
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@ -53,14 +53,14 @@ module testbench;
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv";
string RISCV_DIR = getenvval("RISCV");
string WALLY_DIR = getenvval("WALLY"); // ~/cvw typical
`elsif VCS
import "DPI-C" function string getenv(input string env_name);
string RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
string RISCV_DIR = getenv("RISCV");
string WALLY_DIR = getenv("WALLY");
`else
string RISCV_DIR = "$RISCV"; // "/opt/riscv";
string RISCV_DIR = "$RISCV";
string WALLY_DIR = "$WALLY";
`endif