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Updated email address authorship for my files.

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Rose Thompson 2024-10-15 10:27:53 -05:00
parent 2575a0c40c
commit 8fb1673ab3
60 changed files with 60 additions and 60 deletions
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bin/CModelBTBAccuracy.sh
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#!/bin/bash
###########################################
## Written: ross1728@gmail.com
## Written: rose@rosethompson.net
## Created: 23 October 2023
## Modified:
##

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bin/CModelBranchAccuracy.sh
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#!/bin/bash
###########################################
## Written: ross1728@gmail.com
## Written: rose@rosethompson.net
## Created: 12 March 2023
## Modified:
##

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bin/SeparateBranch.sh
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#!/bin/bash
###########################################
## Written: ross1728@gmail.com
## Written: rose@rosethompson.net
## Created: 12 March 2023
## Modified:
##

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bin/extractFunctionRadix.sh
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## extractFunctionRadix.sh
##
## Written: Rose Thompson
## email: ross1728@gmail.com
## email: rose@rosethompson.net
## Created: March 1, 2021
## Modified: March 10, 2021
##

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bin/parseHPMC.py
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#!/usr/bin/env python3
###########################################
## Written: Rose Thompson ross1728@gmail.com
## Written: Rose Thompson rose@rosethompson.net
## Created: 20 September 2023
## Modified:
##

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bin/wally-tool-chain-install.sh
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###########################################
## Tool chain install script.
##
## Written: Rose Thompson ross1728@gmail.com
## Written: Rose Thompson rose@rosethompson.net
## Created: 18 January 2023
## Modified: 22 January 2023
## Modified: 23 March 2023

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fpga/rvvidaemon/rvvidaemon.c
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///////////////////////////////////////////
// rvvi daemon
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: 31 May 2024
// Modified: 31 May 2024
//

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fpga/src/fpgaTop.sv
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///////////////////////////////////////////
// fpgaTop.sv
//
// Written: ross1728@gmail.com November 17, 2021
// Written: rose@rosethompson.net November 17, 2021
// Modified:
//
// Purpose: This is a top level for the fpga's implementation of wally.

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fpga/src/fpgaTopArtyA7.sv
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///////////////////////////////////////////
// fpgaTop.sv
//
// Written: ross1728@gmail.com November 17, 2021
// Written: rose@rosethompson.net November 17, 2021
// Modified:
//
// Purpose: This is a top level for the fpga's implementation of wally.

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fpga/src/wallypipelinedsocwrapper.sv
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///////////////////////////////////////////
// wallypipelinedsocwrapper.sv
//
// Written: Rose Thompson ross1728@gmail.com 16 June 2023
// Written: Rose Thompson rose@rosethompson.net 16 June 2023
// Modified:
//
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,

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src/cache/cache.sv vendored
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///////////////////////////////////////////
// cache.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 7 July 2021
// Modified: 20 January 2023
//

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src/cache/cacheLRU.sv vendored
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///////////////////////////////////////////
// cacheLRU.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 20 July 2021
// Modified: 20 January 2023
//

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src/cache/cachefsm.sv vendored
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///////////////////////////////////////////
// cachefsm.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 25 August 2021
// Modified: 20 January 2023
//

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src/cache/cacheway.sv vendored
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///////////////////////////////////////////
// cacheway
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 7 July 2021
// Modified: 20 January 2023
//

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src/cache/subcachelineread.sv vendored
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///////////////////////////////////////////
// subcachelineread.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 4 February 2022
// Modified: 20 January 2023
//

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src/ebu/ahbcacheinterface.sv
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///////////////////////////////////////////
// ahbcacheinterface.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 29, 2022
// Modified: 18 January 2023
//

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src/ebu/ahbinterface.sv
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///////////////////////////////////////////
// ahbinterface.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 29, 2022
// Modified: 18 January 2023
//

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src/ebu/buscachefsm.sv
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///////////////////////////////////////////
// busfsm.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: December 29, 2021
// Modified: 18 January 2023
//

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src/ebu/busfsm.sv
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///////////////////////////////////////////
// busfsm.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: December 29, 2021
// Modified: 18 January 2023
//

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src/ebu/controllerinput.sv
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///////////////////////////////////////////
// controllerinput.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 31, 2022
// Modified: 18 January 2023
//

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src/ebu/ebu.sv
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///////////////////////////////////////////
// abhmulticontroller
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 29, 2022
// Modified: 18 January 2023
//

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src/ebu/ebufsmarb.sv
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///////////////////////////////////////////
// ebufsmarb.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 23 January 2023
// Modified: 23 January 2023
//

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src/generic/arrs.sv
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///////////////////////////////////////////
// arrs.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: November 12, 2021
//
// Purpose: resets are typically asynchronous but need to be synchronized to

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src/generic/binencoder.sv
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///////////////////////////////////////////
// binencoder.sv
//
// Written: ross1728@gmail.com November 14, 2022
// Written: rose@rosethompson.net November 14, 2022
//
// Purpose: one-hot to binary encoding.
//

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src/generic/mem/ram1p1rwbe.sv
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// ram1p1r2be.sv
// 1 port sram with byte enables
//
// Written: ross1728@gmail.com
// Written: rose@rosethompson.net
// Created: 3 May 2021
// Modified: 20 January 2023
//

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src/generic/mem/ram1p1rwe.sv
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// ram1p1rwe.sv
// 1 port sram.
//
// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com)
// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net)
// Created: 04 April 2023
//
// Purpose: ram1p1wre, but without byte-enable. Used for icache data.

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src/generic/mem/ram2p1r1wbe.sv
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// ram2p1r1wbe.sv
// 2 port sram.
//
// Written: ross1728@gmail.com May 3, 2021
// Written: rose@rosethompson.net May 3, 2021
// Two port SRAM 1 read port and 1 write port.
// When clk rises Addr and LineWriteData are sampled.
// Following the clk edge read data is output from the sampled Addr.

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src/generic/onehotdecoder.sv
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///////////////////////////////////////////
// onehotdecoder.sv
//
// Written: ross1728@gmail.com July 09, 2021
// Written: rose@rosethompson.net July 09, 2021
// Modified:
//
// Purpose: Bin to one hot decoder. Power of 2 only.

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src/ifu/bpred/RASPredictor.sv
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///////////////////////////////////////////
// RASPredictor.sv
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: 15 February 2021
// Modified: 25 January 2023
//

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src/ifu/bpred/bpred.sv
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///////////////////////////////////////////
// bpred.sv
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: 12 February 2021
// Modified: 19 January 2023
//

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src/ifu/bpred/btb.sv
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///////////////////////////////////////////
// btb.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: February 15, 2021
// Modified: 24 January 2023
//

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src/ifu/bpred/gshare.sv
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// gshare.sv
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
// Modified: 20 February 2023

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src/ifu/bpred/gsharebasic.sv
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// gsharebasic.sv
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
// Modified: 20 February 2023

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src/ifu/bpred/icpred.sv
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///////////////////////////////////////////
// icpred.sv
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: February 26, 2023
// Modified: February 26, 2023
//

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src/ifu/bpred/localaheadbp.sv
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// localaheadbp
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
//
// Purpose: local history branch predictor with ahead pipelining and SRAM memories.

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src/ifu/bpred/localbpbasic.sv
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// localbpbasic
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
//
// Purpose: Local history branch predictor. Basic implementation without any repair and flop memories.

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src/ifu/bpred/localrepairbp.sv
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// localrepairbp
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 15 April 2023
//
// Purpose: Local history branch predictor with speculation and repair using CBH.

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src/ifu/bpred/satCounter2.sv
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// satCounter2.sv
//
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: February 13, 2021
// Modified:
//

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src/ifu/bpred/twoBitPredictor.sv
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// twoBitPredictor.sv
//
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: February 14, 2021
// Modified:
//

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src/ifu/irom.sv
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///////////////////////////////////////////
// irom.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 30 January 2022
// Modified: 18 January 2023
//

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src/ifu/spill.sv
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///////////////////////////////////////////
// spill.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 28 January 2022
// Modified: 19 January 2023
//

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src/lsu/align.sv
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///////////////////////////////////////////
// spill.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 26 October 2023
// Modified: 26 October 2023
//

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src/lsu/atomic.sv
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///////////////////////////////////////////
// atomic.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 31 January 2022
// Modified: 18 January 2023
//

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src/lsu/dtim.sv
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///////////////////////////////////////////
// dtim.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 30 January 2022
// Modified: 18 January 2023
//

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src/lsu/lsu.sv
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
// lsu.sv
//
// Written: David_Harris@hmc.edu, ross1728@gmail.com
// Written: David_Harris@hmc.edu, rose@rosethompson.net
// Created: 9 January 2021
// Modified: 11 January 2023
//

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src/rvvi/csrindextoaddr.sv
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///////////////////////////////////////////
// csrindextoaddr.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 24 January 2024
// Modified: 24 January 2024
//

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src/rvvi/packetizer.sv
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///////////////////////////////////////////
// packetizer.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 21 May 2024
// Modified: 21 May 2024
//

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src/rvvi/priorityaomux.sv
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///////////////////////////////////////////
// priorityaomux.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 24 January 2024
// Modified: 24 January 2024
//

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src/rvvi/regchangedetect.sv
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///////////////////////////////////////////
// regchangedetect.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 24 January 2024
// Modified: 24 January 2024
//

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src/rvvi/rvvisynth.sv
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///////////////////////////////////////////
// rvvisynth.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 23 January 2024
// Modified: 23 January 2024
//

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src/rvvi/triggergen.sv
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///////////////////////////////////////////
// triggergen.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: June 26, 2024
// Modified: June 26, 2024
//

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testbench/common/DCacheFlushFSM.sv
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///////////////////////////////////////////
// DCacheFlushFSM.sv
//
// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
//
// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

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testbench/common/functionName.sv
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///////////////////////////////////////////
// functionName.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
//
// Purpose: decode name of function
//

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testbench/common/loggers.sv
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///////////////////////////////////////////
// loggers.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
//
// Purpose: Log branch instructions, log instruction fetches,

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testbench/common/rvvitbwrapper.sv
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///////////////////////////////////////////
// loggers.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: 24 July 2024
//
// Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench.

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testbench/common/watchdog.sv
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///////////////////////////////////////////
// watchdog.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
//
// Purpose: Detects if the processor is stuck and halts the simulation

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S
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// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 18 August 2023
//

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
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// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 22 August 2023
//

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
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// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 18 August 2023
//

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S
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// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 22 August 2023
//